static int spic_transfer(const u8 *cmd, int n_cmd, u8 *buf, int n_buf, int flag)
{
int retval = -1;
//spic_init();
ra_dbg("cmd(%x): %x %x %x %x , buf:%x len:%x, flag:%s \n",
n_cmd, cmd[0], cmd[1], cmd[2], cmd[3],
(buf)? (*buf) : 0, n_buf,
(flag == SPIC_READ_BYTES)? "read" : "write");
#if defined(CONFIG_RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)||defined(CONFIG_RALINK_SLIC_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
ra_outl(RT2880_SPI_ARB_REG, SPIARB_ARB_EN|(SPIARB_SPI1_ACTIVE_MODE<<1)| SPIARB_SPI0_ACTIVE_MODE);
#if defined(CONFIG_RALINK_SPI_CS1_HIGH_ACTIVE)
ra_and(RT2880_SPI1_CTL_REG, (~SPIARB_SPI1_ACTIVE_MODE));
#else
ra_or(RT2880_SPI1_CTL_REG, (~SPIARB_SPI1_ACTIVE_MODE)&0x01);
#endif
#endif
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | CFG_CLK_DIV | SPICFG_SPICLKPOL );
// assert CS and we are already CLK normal high
ra_and(RT2880_SPICTL_REG, ~(SPICTL_SPIENA_HIGH));
// write command
for (retval = 0; retval < n_cmd; retval++) {
ra_outl(RT2880_SPIDATA_REG, cmd[retval]);
ra_or(RT2880_SPICTL_REG, SPICTL_STARTWR);
if (spic_busy_wait()) {
retval = -1;
goto end_trans;
}
}
// read / write data
if (flag & SPIC_READ_BYTES) {
for (retval = 0; retval < n_buf; retval++) {
ra_or(RT2880_SPICTL_REG, SPICTL_STARTRD);
if (spic_busy_wait())
goto end_trans;
buf[retval] = (u8) ra_inl(RT2880_SPIDATA_REG);
}
}
else if (flag & SPIC_WRITE_BYTES) {
for (retval = 0; retval < n_buf; retval++) {
ra_outl(RT2880_SPIDATA_REG, buf[retval]);
ra_or(RT2880_SPICTL_REG, SPICTL_STARTWR);
if (spic_busy_wait())
goto end_trans;
}
}
end_trans:
// de-assert CS and
ra_or (RT2880_SPICTL_REG, (SPICTL_SPIENA_HIGH));
return retval;
}
int spic_init(void)
{
// GPIO-SPI mode
ra_and(RALINK_REG_GPIOMODE, ~(1 << 1)); //use normal(SPI) mode instead of GPIO mode
/* reset spi block */
ra_or(RT2880_RSTCTRL_REG, RSTCTRL_SPI_RESET);
udelay(1);
ra_and(RT2880_RSTCTRL_REG, ~RSTCTRL_SPI_RESET);
udelay(1);
#if defined(CONFIG_RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)||defined(CONFIG_RALINK_SLIC_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
ra_outl(RT2880_SPI_ARB_REG, SPIARB_ARB_EN|(SPIARB_SPI1_ACTIVE_MODE<<1)| SPIARB_SPI0_ACTIVE_MODE);
ra_outl(RT2880_SPI1_CTL_REG, (~SPIARB_SPI1_ACTIVE_MODE)&0x1);
#endif
ra_outl(RT2880_SPI0_CTL_REG, (~SPIARB_SPI0_ACTIVE_MODE)&0x1);
// FIXME, clk_div should depend on spi-flash.
// mode 0 (SPICLKPOL = 0) & (RXCLKEDGE_FALLING = 0)
// mode 3 (SPICLKPOL = 1) & (RXCLKEDGE_FALLING = 0)
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | CFG_CLK_DIV | SPICFG_SPICLKPOL );
// set idle state
ra_outl(RT2880_SPICTL_REG, SPICTL_HIZSDO | SPICTL_SPIENA_HIGH);
spi_wait_nsec = (8 * 1000 / ((get_surfboard_sysclk() / 1000 / 1000 / CFG_CLK_DIV) )) >> 1 ;
//printk("spi_wait_nsec: %x \n", spi_wait_nsec);
return 0;
}
int spic_init(void)
{
// GPIO-SPI mode
ra_and(RALINK_REG_GPIOMODE, ~(1 << 1)); //use normal(SPI) mode instead of GPIO mode
/* reset spi block */
ra_or(RT2880_RSTCTRL_REG, RSTCTRL_SPI_RESET);
udelay(1);
ra_and(RT2880_RSTCTRL_REG, ~RSTCTRL_SPI_RESET);
udelay(1);
#if defined(CONFIG_RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)||defined(CONFIG_RALINK_SLIC_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
ra_outl(RT2880_SPI_ARB_REG, SPIARB_ARB_EN|(SPIARB_SPI1_ACTIVE_MODE<<1)| SPIARB_SPI0_ACTIVE_MODE);
ra_outl(RT2880_SPI1_CTL_REG, (~SPIARB_SPI1_ACTIVE_MODE)&0x1);
#endif
ra_outl(RT2880_SPI0_CTL_REG, (~SPIARB_SPI0_ACTIVE_MODE)&0x1);
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_RXCLKEDGE_FALLING | SPICFG_TXCLKEDGE_FALLING | CFG_CLK_DIV);
// set idle state
ra_outl(RT2880_SPICTL_REG, SPICTL_HIZSDO | SPICTL_SPIENA_HIGH);
spi_wait_nsec = (8 * 1000 / (128 / (CFG_CLK_DIV+1)) ) >> 1 ;
printk("Ralink SPI flash driver, SPI clock: %dMHz\n", (get_surfboard_sysclk() / 1000000) >> (CFG_CLK_DIV+1));
return 0;
}
int spic_init(void)
{
// use normal(SPI) mode instead of GPIO mode
ra_and(RT2880_GPIOMODE_REG, ~(1 << 1));
#if defined (RT6855_ASIC_BOARD) || defined (RT6855_FPGA_BOARD)
ra_or(RT2880_GPIOMODE_REG, (1 << 11));
#endif
// reset spi block
ra_or(RT2880_RSTCTRL_REG, RSTCTRL_SPI_RESET);
udelay(1);
ra_and(RT2880_RSTCTRL_REG, ~RSTCTRL_SPI_RESET);
#if defined(RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
RT2880_REG(RT2880_SPI_ARB_REG) = SPIARB_ARB_EN | (SPIARB_SPI1_ACTIVE_MODE <<1) | SPIARB_SPI0_ACTIVE_MODE;
RT2880_REG(RT2880_SPI0_CTL_REG) = (~SPIARB_SPI0_ACTIVE_MODE)&0x1; //disable first
RT2880_REG(RT2880_SPI1_CTL_REG) = (~SPIARB_SPI1_ACTIVE_MODE)&0x1; //disable first
#endif
// FIXME, clk_div should depend on spi-flash.
#ifdef ADDR_4B // use 4 byte address mode
ra_outl(RT2880_SPI0_CFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | SPICFG_SPICLK_DIV8 | SPICFG_SPICLKPOL | SPICFG_ADDRMODE);
#else
ra_outl(RT2880_SPI0_CFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | SPICFG_SPICLK_DIV8 | SPICFG_SPICLKPOL);
#endif
// set idle state
ra_outl(RT2880_SPI0_CTL_REG, SPICTL_HIZSDO | SPICTL_SPIENA_HIGH);
spi_wait_nsec = (8 * 1000 / ((mips_bus_feq / 1000 / 1000 / SPICFG_SPICLK_DIV8) )) >> 1 ;
printf("spi_wait_nsec: %x \n", spi_wait_nsec);
return 0;
}
/**
* clear NFC and flash chip.
*/
static int nfc_all_reset(void)
{
int retry;
// reset controller
ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) | 0x02); //clear data buffer
ra_outl(NFC_CTRL, ra_inl(NFC_CTRL) & ~0x02); //clear data buffer
CLEAR_INT_STATUS();
retry = READ_STATUS_RETRY;
while ((ra_inl(NFC_INT_ST) & 0x02) != 0x02 && retry--);
if (retry <= 0) {
printf("%s: clean buffer fail\n", __func__);
return -1;
}
retry = READ_STATUS_RETRY;
while ((ra_inl(NFC_STATUS) & 0x1) != 0x0 && retry--) { //fixme, controller is busy ?
udelay(1);
}
if (retry <= 0) {
printf("%s: controller is still busy?\n");
return -1;
}
return nfc_chip_reset();
}
/*
* @cmd: command and address
* @n_cmd: size of command, in bytes
* @buf: buffer into which data will be read/written
* @n_buf: size of buffer, in bytes
* @flag: tag as READ/WRITE
*
* @return: if write_onlu, -1 means write fail, or return writing counter.
* @return: if read, -1 means read fail, or return reading counter.
*/
static int spic_transfer(const u8 *cmd, int n_cmd, u8 *buf, int n_buf, int flag)
{
int retval = -1;
/*
ra_dbg("cmd(%x): %x %x %x %x , buf:%x len:%x, flag:%s \n",
n_cmd, cmd[0], cmd[1], cmd[2], cmd[3],
(buf)? (*buf) : 0, n_buf,
(flag == SPIC_READ_BYTES)? "read" : "write");
*/
// assert CS and we are already CLK normal high
ra_and(RT2880_SPI0_CTL_REG, ~(SPICTL_SPIENA_HIGH));
// write command
for (retval = 0; retval < n_cmd; retval++) {
ra_outl(RT2880_SPI0_DATA_REG, cmd[retval]);
ra_or(RT2880_SPI0_CTL_REG, SPICTL_STARTWR);
if (spic_busy_wait()) {
retval = -1;
goto end_trans;
}
}
// read / write data
if (flag & SPIC_READ_BYTES) {
for (retval = 0; retval < n_buf; retval++) {
ra_or(RT2880_SPI0_CTL_REG, SPICTL_STARTRD);
#ifndef READ_BY_PAGE
if (n_cmd != 1 && (retval & 0xffff) == 0) {
printf(".");
}
#endif
if (spic_busy_wait()) {
printf("\n");
goto end_trans;
}
buf[retval] = (u8) ra_inl(RT2880_SPI0_DATA_REG);
}
}
else if (flag & SPIC_WRITE_BYTES) {
for (retval = 0; retval < n_buf; retval++) {
ra_outl(RT2880_SPI0_DATA_REG, buf[retval]);
ra_or(RT2880_SPI0_CTL_REG, SPICTL_STARTWR);
if (spic_busy_wait()) {
goto end_trans;
}
}
}
end_trans:
// de-assert CS and
ra_or (RT2880_SPI0_CTL_REG, (SPICTL_SPIENA_HIGH));
return retval;
}
void spic_init(void)
{
u32 clk_sys, clk_div, reg;
#if defined (CONFIG_RALINK_MT7621)
clk_sys = 125; /* bclk = 125MHz */
#if defined (CONFIG_MTD_SPI_FAST_CLOCK)
clk_div = 4; /* bclk/4 -> 31.25 MHz */
#else
clk_div = 5; /* bclk/5 -> 25 MHz */
#endif
#elif defined (CONFIG_RALINK_MT7628)
clk_sys = get_surfboard_sysclk() / 1000000;
#if defined (CONFIG_MTD_SPI_FAST_CLOCK)
clk_div = 5; /* hclk/5 -> 40 MHz */
#else
clk_div = 8; /* hclk/8 -> 25 MHz */
#endif
#endif
reg = ra_inl(SPI_REG_MASTER);
reg &= ~(0x7);
reg &= ~(0x0fff << 16);
reg |= ((clk_div - 2) << 16);
ra_outl(SPI_REG_MASTER, reg);
#ifdef TEST_CS1_FLASH
#if defined (CONFIG_RALINK_MT7628)
ra_and(RALINK_REG_GPIOMODE, ~(3 << 4));
#endif
ra_or(SPI_REG_MASTER, (1 << 29));
#endif
printk("Ralink SPI flash driver, SPI clock: %dMHz\n", clk_sys / clk_div);
}
void spic_init(void)
{
#if defined (MT7621_ASIC_BOARD) || defined (MT7628_ASIC_BOARD)
u32 clk_sys, clk_div, reg;
clk_sys = mips_bus_feq / 1000000;
#if defined (MT7621_ASIC_BOARD)
// hclk = 220 MHz
#ifdef SPI_FAST_CLOCK
clk_div = 5; /* hclk/5 -> 44.0 MHz */
#else
clk_div = 7; /* hclk/7 -> 31.4 MHz */
#endif
#else
// hclk = 193/191 MHz
#ifdef SPI_FAST_CLOCK
clk_div = 4; /* hclk/4 -> 48.3 MHz */
#else
clk_div = 6; /* hclk/6 -> 32.2 MHz */
#endif
#endif
reg = ra_inl(SPI_REG_MASTER);
reg &= ~(0x7);
reg &= ~(0xfff << 16);
reg |= ((clk_div - 2) << 16);
ra_outl(SPI_REG_MASTER, reg);
printf("%s SPI flash driver, SPI clock: %dMHz\n", RLT_MTK_VENDOR_NAME, clk_sys / clk_div);
#elif defined (RT6855_ASIC_BOARD) || defined (RT6855_FPGA_BOARD)
// enable SMC bank 0 alias addressing
ra_or(RALINK_SYSCTL_BASE + 0x38, 0x80000000);
#endif
}
/**
* reset nand chip
*/
static int nfc_chip_reset(void)
{
int status;
//ra_dbg("%s:\n", __func__);
// reset nand flash
ra_outl(NFC_CMD1, 0xff);
ra_outl(NFC_ADDR, 0xfffffff);
ra_outl(NFC_CONF, 0x0141 | (CFG_ADDR_CYCLE << 16));
status = nfc_wait_ready(0); //erase wait 5us
if (status & NAND_STATUS_FAIL) {
printf("%s: fail\n", __func__);
return -1;
}
return 0;
}
static void gpio0_low(void)
{
//u32 gpio_mode, pol, data, dir;
//gpio_mode = ra_inl(RALINK_SYSCTL_BASE + 0x60);
//data = ra_inl(RALINK_PIO_BASE+0x20);
//dir = ra_inl(RALINK_PIO_BASE+0x24);
//pol = ra_inl(RALINK_PIO_BASE+0x28);
//printf("%x %x %x %x\n", gpio_mode, data, dir, pol);
ra_outl(RALINK_PIO_BASE+0x20, 0);
}
/** NOTICE: only called by nfc_wait_ready().
* @return -1, nfc can not get transction done
* @return 0, ok.
*/
static int nfc_read_status(char *status)
{
unsigned long cmd1, conf;
int int_st, nfc_st;
int retry;
cmd1 = 0x70;
conf = 0x000101 | (1 << 20);
//FIXME, should we check nfc status?
CLEAR_INT_STATUS();
ra_outl(NFC_CMD1, cmd1);
ra_outl(NFC_CONF, conf);
/* FIXME,
* 1. since we have no wired ready signal, directly
* calling this function is not gurantee to read right status under ready state.
* 2. the other side, we can not determine how long to become ready, this timeout retry is nonsense.
* 3. SUGGESTION: call nfc_read_status() from nfc_wait_ready(),
* that is aware about caller (in sementics) and has snooze plused nfc ND_DONE.
*/
retry = READ_STATUS_RETRY;
do {
nfc_st = ra_inl(NFC_STATUS);
int_st = ra_inl(NFC_INT_ST);
udelay(1);
} while (!(int_st & INT_ST_RX_BUF_RDY) && retry--);
if (!(int_st & INT_ST_RX_BUF_RDY)) {
printf("%s: NFC fail, int_st(%x), retry:%x. nfc:%x, reset nfc and flash.\n",
__func__, int_st, retry, nfc_st);
nfc_all_reset();
*status = NAND_STATUS_FAIL;
return -1;
}
*status = (char)(le32_to_cpu(ra_inl(NFC_DATA)) & 0x0ff);
return 0;
}
unsigned long ranand_init(void)
{
//maks sure gpio-0 is input
ra_outl(RALINK_PIO_BASE+0x24, ra_inl(RALINK_PIO_BASE+0x24) & ~0x01);
//set WP to high
ra_or(NFC_CTRL, 0x01);
if (nfc_all_reset() != 0)
return -1;
return CFG_CHIPSIZE;
}
int spic_init(void)
{
// use normal(SPI) mode instead of GPIO mode
ra_and(RT2880_GPIOMODE_REG, ~(1 << 1));
// reset spi block
ra_or(RT2880_RSTCTRL_REG, RSTCTRL_SPI_RESET);
udelay(1);
ra_and(RT2880_RSTCTRL_REG, ~RSTCTRL_SPI_RESET);
// FIXME, clk_div should depend on spi-flash.
ra_outl(RT2880_SPICFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | SPICFG_SPICLK_DIV4 | SPICFG_SPICLKPOL);
// set idle state
ra_outl(RT2880_SPICTL_REG, SPICTL_HIZSDO | SPICTL_SPIENA_HIGH);
spi_wait_nsec = (8 * 1000 / ((mips_bus_feq / 1000 / 1000 / SPICFG_SPICLK_DIV4) )) >> 1 ;
printf("spi_wait_nsec: %x \n", spi_wait_nsec);
return 0;
}
int spic_init(void)
{
// use normal(SPI) mode instead of GPIO mode
#if defined (RT6855_ASIC_BOARD) || defined (RT6855_FPGA_BOARD)
ra_or(RT2880_GPIOMODE_REG, (1 << 11));
#elif defined (MT7620_ASIC_BOARD) || defined (MT7620_FPGA_BOARD)
ra_and(RT2880_GPIOMODE_REG, ~(1 << 11));
#else
ra_and(RT2880_GPIOMODE_REG, ~(1 << 1));
#endif
// reset spi block
ra_or(RT2880_RSTCTRL_REG, RSTCTRL_SPI_RESET);
udelay(1);
ra_and(RT2880_RSTCTRL_REG, ~RSTCTRL_SPI_RESET);
udelay(1);
#if defined(RALINK_VITESSE_SWITCH_CONNECT_SPI_CS1)
/* config ARB and set the low or high active correctly according to the device */
RT2880_REG(RT2880_SPI_ARB_REG) = SPIARB_ARB_EN | (SPIARB_SPI1_ACTIVE_MODE <<1) | SPIARB_SPI0_ACTIVE_MODE;
RT2880_REG(RT2880_SPI0_CTL_REG) = (~SPIARB_SPI0_ACTIVE_MODE)&0x1; //disable first
RT2880_REG(RT2880_SPI1_CTL_REG) = (~SPIARB_SPI1_ACTIVE_MODE)&0x1; //disable first
#endif
#if !defined(COMMAND_MODE)
ra_outl(RT2880_SPI0_CFG_REG, SPICFG_MSBFIRST | SPICFG_RXCLKEDGE_FALLING | SPICFG_TXCLKEDGE_FALLING | CFG_CLK_DIV);
#else
ra_outl(RT2880_SPI0_CFG_REG, SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING | SPICFG_SPICLKPOL | CFG_CLK_DIV);
#endif
// set idle state
ra_outl(RT2880_SPI0_CTL_REG, SPICTL_HIZSDO | SPICTL_SPIENA_HIGH);
spi_wait_nsec = (8 * 1000 / (128 / (CFG_CLK_DIV+1)) ) >> 1 ;
printf("%s SPI flash driver, SPI clock: %dMHz\n", RLT_MTK_VENDOR_NAME, (mips_bus_feq / 1000000) >> (CFG_CLK_DIV+1));
return 0;
}
/**
* generic function to get data from flash.
* @return data length reading from flash.
*/
static int _ra_nand_pull_data(char *buf, int len)
{
#ifdef RW_DATA_BY_BYTE
char *p = buf;
#else
__u32 *p = (__u32 *)buf;
#endif
int retry, int_st;
unsigned int ret_data;
int ret_size;
retry = READ_STATUS_RETRY;
while (len > 0) {
int_st = ra_inl(NFC_INT_ST);
if (int_st & INT_ST_RX_BUF_RDY) {
ret_data = ra_inl(NFC_DATA);
ra_outl(NFC_INT_ST, INT_ST_RX_BUF_RDY);
#ifdef RW_DATA_BY_BYTE
ret_size = sizeof(unsigned int);
ret_size = min(ret_size, len);
len -= ret_size;
while (ret_size-- > 0) {
//nfc is little endian
*p++ = ret_data & 0x0ff;
ret_data >>= 8;
}
#else
ret_size = min(len, 4);
len -= ret_size;
if (ret_size == 4)
*p++ = ret_data;
else {
__u8 *q = (__u8 *)p;
while (ret_size-- > 0) {
*q++ = ret_data & 0x0ff;
ret_data >>= 8;
}
p = (__u32 *)q;
}
#endif
}
else if (int_st & INT_ST_ND_DONE) {
static void gpio0_high(void)
{
ra_outl(RALINK_PIO_BASE+0x20, 1);
}
