void Lcd_t::Init(void) {
BckLt.Init(LCD_BCKLT_GPIO, LCD_BCKLT_PIN, LCD_BCKLT_TMR, LCD_BCKLT_CHNL, LCD_TOP_BRIGHTNESS);
// Remap Timer15 to PB14 & PB15
AFIO->MAPR2 |= 0x00000001;
// ==== GPIOs ====
// Configure LCD_XRES, LCD_XCS, LCD_SCLK & LCD_SDA as Push-Pull output
PinSetupOut(LCD_GPIO, LCD_XRES, omPushPull);
PinSetupOut(LCD_GPIO, LCD_XRES, omPushPull);
PinSetupOut(LCD_GPIO, LCD_XCS, omPushPull);
PinSetupOut(LCD_GPIO, LCD_SCLK, omPushPull);
PinSetupOut(LCD_GPIO, LCD_SDA, omPushPull);
// ========================= Init LCD ======================================
SCLK_Lo();
XCS_Hi();
// Reset display
XRES_Lo();
chThdSleepMilliseconds(7);
XRES_Hi();
WriteCmd(0xAF); // display ON
// Reset display again
XRES_Lo();
chThdSleepMilliseconds(7);
XRES_Hi();
chThdSleepMilliseconds(7);
// Initial commands
WriteCmd(0xAF); // display ON
WriteCmd(0xA4); // Set normal display mode
WriteCmd(0x2F); // Charge pump on
WriteCmd(0x40); // Set start row address = 0
WriteCmd(0xC8); // Mirror Y axis
//WriteCmd(0xA1); // Mirror X axis
// Set x=0, y=0
WriteCmd(0xB0); // Y axis initialization
WriteCmd(0x10); // X axis initialisation1
WriteCmd(0x00); // X axis initialisation2
Cls(); // clear LCD buffer
// ====================== Switch to USART + DMA ============================
PinSetupAlterFuncOutput(LCD_GPIO, LCD_SCLK, omPushPull);
PinSetupAlterFuncOutput(LCD_GPIO, LCD_SDA, omPushPull);
// Workaround hardware bug with disabled CK3 when SPI2 is enabled
SPI2->CR2 |= SPI_CR2_SSOE;
// ==== USART init ==== clock enabled, idle low, first edge, enable last bit pulse
rccEnableUSART3(FALSE);
USART3->CR1 = USART_CR1_UE; // Enable
USART3->BRR = Clk.APB1FreqHz / LCD_UART_SPEED;
USART3->CR2 = USART_CR2_CLKEN | USART_CR2_LBCL; // Enable clock, enable last bit clock
USART3->CR1 = USART_CR1_UE | USART_CR1_M | USART_CR1_TE;
USART3->CR3 = USART_CR3_DMAT; // Enable DMA at transmitter
// DMA
dmaStreamAllocate (LCD_DMA, IRQ_PRIO_LOW, nullptr, NULL);
dmaStreamSetPeripheral(LCD_DMA, &USART3->DR);
dmaStreamSetMemory0 (LCD_DMA, IBuf);
dmaStreamSetTransactionSize(LCD_DMA, LCD_VIDEOBUF_SIZE);
dmaStreamSetMode (LCD_DMA, LCD_DMA_TX_MODE);
// Start transmission
XCS_Lo();
dmaStreamEnable(LCD_DMA);
}
/**
* @brief Low level serial driver configuration and (re)start.
*
* @param[in] sdp pointer to a @p SerialDriver object
* @param[in] config the architecture-dependent serial driver configuration.
* If this parameter is set to @p NULL then a default
* configuration is used.
*
* @notapi
*/
void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
if (config == NULL)
config = &default_config;
if (sdp->state == SD_STOP) {
#if STM32_SERIAL_USE_USART1
if (&SD1 == sdp) {
rccEnableUSART1(FALSE);
nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_USART2
if (&SD2 == sdp) {
rccEnableUSART2(FALSE);
nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_USART3
if (&SD3 == sdp) {
rccEnableUSART3(FALSE);
nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_UART4
if (&SD4 == sdp) {
rccEnableUART4(FALSE);
nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_UART5
if (&SD5 == sdp) {
rccEnableUART5(FALSE);
nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_USART6
if (&SD6 == sdp) {
rccEnableUSART6(FALSE);
nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_UART7
if (&SD7 == sdp) {
rccEnableUART7(FALSE);
nvicEnableVector(STM32_UART7_NUMBER, STM32_SERIAL_UART7_PRIORITY);
}
#endif
#if STM32_SERIAL_USE_UART8
if (&SD8 == sdp) {
rccEnableUART8(FALSE);
nvicEnableVector(STM32_UART8_NUMBER, STM32_SERIAL_UART8_PRIORITY);
}
#endif
}
usart_init(sdp, config);
}
/**
* @brief Low level serial driver configuration and (re)start.
*
* @param[in] sdp pointer to a @p SerialDriver object
* @param[in] config the architecture-dependent serial driver configuration.
* If this parameter is set to @p NULL then a default
* configuration is used.
*
* @notapi
*/
void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
if (config == NULL)
config = &default_config;
if (sdp->state == SD_STOP) {
#if STM32_SERIAL_USE_USART1
if (&SD1 == sdp) {
rccEnableUSART1(FALSE);
}
#endif
#if STM32_SERIAL_USE_USART2
if (&SD2 == sdp) {
rccEnableUSART2(FALSE);
}
#endif
#if STM32_SERIAL_USE_USART3
if (&SD3 == sdp) {
rccEnableUSART3(FALSE);
}
#endif
#if STM32_SERIAL_USE_UART4
if (&SD4 == sdp) {
rccEnableUART4(FALSE);
}
#endif
#if STM32_SERIAL_USE_UART5
if (&SD5 == sdp) {
rccEnableUART5(FALSE);
}
#endif
#if STM32_SERIAL_USE_USART6
if (&SD6 == sdp) {
rccEnableUSART6(FALSE);
}
#endif
#if STM32_SERIAL_USE_UART7
if (&SD7 == sdp) {
rccEnableUART7(FALSE);
}
#endif
#if STM32_SERIAL_USE_UART8
if (&SD8 == sdp) {
rccEnableUART8(FALSE);
}
#endif
#if STM32_SERIAL_USE_LPUART1
if (&LPSD1 == sdp) {
rccEnableLPUART1(FALSE);
}
#endif
}
usart_init(sdp, config);
}
void usart_support_init(void)
{
SD1.usart = USART1;
SD1.tx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART1_TX_DMA_STREAM);
dmaStreamAllocate(SD1.tx.dma, STM32_SERIAL_USART1_PRIORITY,
(stm32_dmaisr_t)usart_tx_dma_isr, &SD1.tx);
SD1.rx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART1_RX_DMA_STREAM);
dmaStreamAllocate(SD1.rx.dma, STM32_SERIAL_USART1_PRIORITY,
(stm32_dmaisr_t)usart_rx_dma_isr, &SD1.rx);
SD1.dmamode = STM32_DMA_CR_CHSEL(USART1_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SERIAL_USART1_DMA_PRIORITY);
usart_support_init_tx(&SD1);
usart_support_init_rx(&SD1);
rccEnableUSART1(FALSE);
SD3.usart = USART3;
SD3.tx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART3_TX_DMA_STREAM);
dmaStreamAllocate(SD3.tx.dma, STM32_SERIAL_USART3_PRIORITY,
(stm32_dmaisr_t)usart_tx_dma_isr, &SD3.tx);
SD3.rx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART3_RX_DMA_STREAM);
dmaStreamAllocate(SD3.rx.dma, STM32_SERIAL_USART3_PRIORITY,
(stm32_dmaisr_t)usart_rx_dma_isr, &SD3.rx);
SD3.dmamode = STM32_DMA_CR_CHSEL(USART3_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SERIAL_USART3_DMA_PRIORITY);
usart_support_init_tx(&SD3);
usart_support_init_rx(&SD3);
rccEnableUSART3(FALSE);
SD6.usart = USART6;
SD6.tx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART6_TX_DMA_STREAM);
dmaStreamAllocate(SD6.tx.dma, STM32_SERIAL_USART6_PRIORITY,
(stm32_dmaisr_t)usart_tx_dma_isr, &SD6.tx);
SD6.rx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART6_RX_DMA_STREAM);
dmaStreamAllocate(SD6.rx.dma, STM32_SERIAL_USART6_PRIORITY,
(stm32_dmaisr_t)usart_rx_dma_isr, &SD6.rx);
SD6.dmamode = STM32_DMA_CR_CHSEL(USART6_TX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_SERIAL_USART6_DMA_PRIORITY);
usart_support_init_tx(&SD6);
usart_support_init_rx(&SD6);
rccEnableUSART6(FALSE);
}
/**
* @brief Configures and activates the UART peripheral.
*
* @param[in] uartp pointer to the @p UARTDriver object
*
* @notapi
*/
void uart_lld_start(UARTDriver *uartp) {
if (uartp->state == UART_STOP) {
#if STM32_UART_USE_USART1
if (&UARTD1 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
rccEnableUSART1(FALSE);
nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_USART2
if (&UARTD2 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
rccEnableUSART2(FALSE);
nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_USART3
if (&UARTD3 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
rccEnableUSART3(FALSE);
nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_UART4
if (&UARTD4 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
rccEnableUART4(FALSE);
nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_UART5
if (&UARTD5 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
rccEnableUART5(FALSE);
nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_USART6
if (&UARTD6 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
rccEnableUSART6(FALSE);
nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_UART7
if (&UARTD7 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_UART7_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_UART7_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
rccEnableUART7(FALSE);
nvicEnableVector(STM32_UART7_NUMBER, STM32_UART_UART7_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_UART8
if (&UARTD8 == uartp) {
bool b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_UART8_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_UART8_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
osalDbgAssert(!b, "stream already allocated");
rccEnableUART8(FALSE);
nvicEnableVector(STM32_UART8_NUMBER, STM32_UART_UART8_IRQ_PRIORITY);
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY);
}
#endif
/* Static DMA setup, the transfer size depends on the USART settings,
it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR);
dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR);
uartp->rxbuf = 0;
}
uartp->rxstate = UART_RX_IDLE;
uartp->txstate = UART_TX_IDLE;
usart_start(uartp);
}
/**
* @brief Configures and activates the UART peripheral.
*
* @param[in] uartp pointer to the @p UARTDriver object
*
* @notapi
*/
void uart_lld_start(UARTDriver *uartp) {
uartp->dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE;
if (uartp->state == UART_STOP) {
#if STM32_UART_USE_USART1
if (&UARTD1 == uartp) {
bool_t b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
rccEnableUSART1(FALSE);
nvicEnableVector(STM32_USART1_NUMBER,
CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_USART2
if (&UARTD2 == uartp) {
bool_t b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
rccEnableUSART2(FALSE);
nvicEnableVector(STM32_USART2_NUMBER,
CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_USART3
if (&UARTD3 == uartp) {
bool_t b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
rccEnableUSART3(FALSE);
nvicEnableVector(STM32_USART3_NUMBER,
CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
}
#endif
/* Static DMA setup, the transfer size depends on the USART settings,
it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR);
dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR);
uartp->rxbuf = 0;
}
uartp->rxstate = UART_RX_IDLE;
uartp->txstate = UART_TX_IDLE;
usart_start(uartp);
}
/**
* @brief Configures and activates the UART peripheral.
*
* @param[in] uartp pointer to the @p UARTDriver object
*
* @notapi
*/
void uart_lld_start(UARTDriver *uartp) {
if (uartp->state == UART_STOP) {
#if STM32_UART_USE_USART1
if (&UARTD1 == uartp) {
bool_t b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART1_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated");
rccEnableUSART1(FALSE);
nvicEnableVector(STM32_USART1_NUMBER,
CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_USART2
if (&UARTD2 == uartp) {
bool_t b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART2_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated");
rccEnableUSART2(FALSE);
nvicEnableVector(STM32_USART2_NUMBER,
CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_USART3
if (&UARTD3 == uartp) {
bool_t b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART3_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated");
rccEnableUSART3(FALSE);
nvicEnableVector(STM32_USART3_NUMBER,
CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_UART4
if (&UARTD4 == uartp) {
bool_t b;
chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
"uart_lld_start(), #7",
"specified invalid bits in UART4 CR2 register settings");
chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
"uart_lld_start(), #8",
"specified invalid bits in UART4 CR3 register settings");
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #9", "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_UART4_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #10", "stream already allocated");
rccEnableUART4(FALSE);
nvicEnableVector(STM32_UART4_NUMBER,
CORTEX_PRIORITY_MASK(STM32_UART_UART4_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_UART5
if (&UARTD5 == uartp) {
bool_t b;
chDbgAssert((uartp->config->cr2 & STM32_UART45_CR2_CHECK_MASK) == 0,
"uart_lld_start(), #11",
"specified invalid bits in UART5 CR2 register settings");
chDbgAssert((uartp->config->cr3 & STM32_UART45_CR3_CHECK_MASK) == 0,
"uart_lld_start(), #12",
"specified invalid bits in UART5 CR3 register settings");
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #13", "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_UART5_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #14", "stream already allocated");
rccEnableUART5(FALSE);
nvicEnableVector(STM32_UART5_NUMBER,
CORTEX_PRIORITY_MASK(STM32_UART_UART5_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY);
}
#endif
#if STM32_UART_USE_USART6
if (&UARTD6 == uartp) {
bool_t b;
b = dmaStreamAllocate(uartp->dmarx,
STM32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_rx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #15", "stream already allocated");
b = dmaStreamAllocate(uartp->dmatx,
STM32_UART_USART6_IRQ_PRIORITY,
(stm32_dmaisr_t)uart_lld_serve_tx_end_irq,
(void *)uartp);
chDbgAssert(!b, "uart_lld_start(), #16", "stream already allocated");
rccEnableUSART6(FALSE);
nvicEnableVector(STM32_USART6_NUMBER,
CORTEX_PRIORITY_MASK(STM32_UART_USART6_IRQ_PRIORITY));
uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) |
STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY);
}
#endif
/* Static DMA setup, the transfer size depends on the USART settings,
it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/
if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M)
uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD;
dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR);
dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR);
uartp->rxbuf = 0;
}
uartp->rxstate = UART_RX_IDLE;
uartp->txstate = UART_TX_IDLE;
usart_start(uartp);
}
void Lcd_t::Init() {
// ==== Backlight: Timer15 Ch2 ====
// Setup pin
PinSetupAlterFuncOutput(LCD_GPIO, LCD_BCKLT, omPushPull, ps50MHz);
// Remap Timer15 to PB14 & PB15
AFIO->MAPR2 |= 0x00000001;
// Setup timer15
rccEnableAPB2(RCC_APB2ENR_TIM15EN, false);
TIM15->CR1 = 0x01; // Enable timer
TIM15->CR2 = 0;
TIM15->PSC = 0; // Do not divide input freq
TIM15->ARR = 100; // Autoreload register: full brightness=100
TIM15->BDTR = 0xC000; // Main output Enable
TIM15->CCMR1 = 0x6000; // PWM mode1 on Ch2 enabled
TIM15->CCER = 0x0010; // Output2 enabled, polarity not inverted
BackligthValue = 0;
// ==== GPIOs ====
// Configure LCD_XRES, LCD_XCS, LCD_SCLK & LCD_SDA as Push-Pull output
InitGpios();
// ========================= Init LCD ======================================
SCLK_Lo();
XCS_Hi();
// Reset display
XRES_Lo();
chThdSleepMilliseconds(9);
XRES_Hi();
WriteCmd(0xAF); // display ON
// Reset display again
XRES_Lo();
chThdSleepMilliseconds(7);
XRES_Hi();
chThdSleepMilliseconds(7);
// Initial commands
WriteCmd(0xAF); // display ON
WriteCmd(0xA4); // Set normal display mode
WriteCmd(0x2F); // Charge pump on
WriteCmd(0x40); // Set start row address = 0
// WriteCmd(0xC8); // mirror Y axis
// WriteCmd(0xA1); // Mirror X axis
// Set x=0, y=0
WriteCmd(0xB3); // Y axis initialization
WriteCmd(0x10); // X axis initialisation1
WriteCmd(0x08); // X axis initialisation2
Cls(); // clear LCD buffer
draw_mode = OVERWRITE;
// ====================== Switch to USART + DMA ============================
#ifdef ENABLE_DMAUSART_MODE
PinSetupAlterFuncOutput(LCD_GPIO, LCD_SCLK, omPushPull, ps50MHz);
PinSetupAlterFuncOutput(LCD_GPIO, LCD_SDA, omPushPull, ps50MHz);
// Workaround hardware bug with disabled CK3 when SPI2 is enabled
SPI2->CR2 |= SPI_CR2_SSOE;
// ==== USART init ====
rccEnableUSART3(false);
// Usart clock: enabled, idle low, first edge, enable last bit pulse
// Usart itself
LCD_USART->BRR = Clk.APB1FreqHz / 100000;
LCD_USART->CR1 = USART_CR1_TE | /* Transmitter enabled */ \
USART_CR1_M; /* 9 bit */
LCD_USART->CR2 = USART_CR2_CLKEN | \
USART_CR2_LBCL;
LCD_USART->CR3 = USART_CR3_DMAT; // Enable DMA at transmitter
LCD_USART->CR1 |= USART_CR1_UE; // Enable USART
// ==== DMA ====
rccEnableDMA1();
dmaStreamAllocate(LCD_DMA, IRQ_PRIO_MEDIUM, LcdDmaCompIrq, NULL);
dmaStreamSetPeripheral(LCD_DMA, &USART3->DR);
dmaStreamSetMemory0(LCD_DMA, (uint32_t)&IBuf[0]);
dmaStreamSetMode (LCD_DMA, LCD_DMA_MODE);
// Start transmission
XCS_Lo();
// DMA_Cmd(DMA1_Channel2, ENABLE); // Enable USARTy DMA TX Channel
#else
for(int i=0; i < 864; i++) WriteData(0x00); // Clear all screen
#endif
Backlight(0);
chThdCreateStatic(waLcdThread, sizeof(waLcdThread), NORMALPRIO, (tfunc_t)LcdThread, NULL);
}
void Lcd_t::Init(void) {
BckLt.Init();
// ==== GPIOs ====
// Configure LCD_XRES, LCD_XCS, LCD_SCLK & LCD_SDA as Push-Pull output
PinSetupOut(LCD_GPIO, LCD_XRES, omPushPull);
PinSetupOut(LCD_GPIO, LCD_XCS, omPushPull);
PinSetupOut(LCD_GPIO, LCD_SCLK, omPushPull);
PinSetupOut(LCD_GPIO, LCD_SDA, omPushPull);
// ========================= Init LCD ======================================
SCLK_Lo();
XCS_Hi();
// Reset display
XRES_Lo();
chThdSleepMilliseconds(7);
XRES_Hi();
IWriteCmd(0xAF); // display ON
// Reset display again
XRES_Lo();
chThdSleepMilliseconds(7);
XRES_Hi();
chThdSleepMilliseconds(7);
// Initial commands
IWriteCmd(0xAF); // display ON
IWriteCmd(0xA4); // Set normal display mode
IWriteCmd(0x2F); // Charge pump on
IWriteCmd(0x40); // Set start row address = 0
#if LCD_MIRROR_Y_AXIS
IWriteCmd(0xC8); // Mirror Y axis
#endif
#if LCD_MIRROR_X_AXIS
IWriteCmd(0xA1); // Mirror X axis
#endif
// Set x=0, y=0
IWriteCmd(0xB0); // Y axis initialization
IWriteCmd(0x10); // X axis initialisation1
IWriteCmd(0x00); // X axis initialisation2
Cls();
#if LCD_DMA_BASED // ================ Switch to USART + DMA ====================
PinSetupAlterFunc(LCD_GPIO, LCD_SCLK, omPushPull, pudNone, AF7, ps40MHz);
PinSetupAlterFunc(LCD_GPIO, LCD_SDA, omPushPull, pudNone, AF7, ps40MHz);
// ==== USART init ==== clock enabled, idle low, first edge, enable last bit pulse
rccEnableUSART3(FALSE);
USART3->CR1 = USART_CR1_UE; // Enable
USART3->BRR = Clk.APB1FreqHz / LCD_UART_SPEED;
USART3->CR2 = USART_CR2_CLKEN | USART_CR2_LBCL; // Enable clock, enable last bit clock
USART3->CR1 = USART_CR1_UE | USART_CR1_M | USART_CR1_TE;
USART3->CR3 = USART_CR3_DMAT; // Enable DMA at transmitter
// DMA
dmaStreamAllocate (LCD_DMA, IRQ_PRIO_LOW, nullptr, NULL);
dmaStreamSetPeripheral(LCD_DMA, &USART3->DR);
dmaStreamSetMemory0 (LCD_DMA, IBuf);
dmaStreamSetTransactionSize(LCD_DMA, LCD_VIDEOBUF_SIZE);
dmaStreamSetMode (LCD_DMA, LCD_DMA_TX_MODE);
// Start transmission
XCS_Lo();
dmaStreamEnable(LCD_DMA);
#else
#endif
chSemInit(&semLcd, 1);
}
