/** * @brief Low level serial driver configuration and (re)start. * * @param[in] sdp pointer to a @p SerialDriver object * @param[in] config the architecture-dependent serial driver configuration. * If this parameter is set to @p NULL then a default * configuration is used. * * @notapi */ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { if (config == NULL) config = &default_config; if (sdp->state == SD_STOP) { #if STM32_SERIAL_USE_USART1 if (&SD1 == sdp) { rccEnableUSART1(FALSE); nvicEnableVector(STM32_USART1_NUMBER, STM32_SERIAL_USART1_PRIORITY); } #endif #if STM32_SERIAL_USE_USART2 if (&SD2 == sdp) { rccEnableUSART2(FALSE); nvicEnableVector(STM32_USART2_NUMBER, STM32_SERIAL_USART2_PRIORITY); } #endif #if STM32_SERIAL_USE_USART3 if (&SD3 == sdp) { rccEnableUSART3(FALSE); nvicEnableVector(STM32_USART3_NUMBER, STM32_SERIAL_USART3_PRIORITY); } #endif #if STM32_SERIAL_USE_UART4 if (&SD4 == sdp) { rccEnableUART4(FALSE); nvicEnableVector(STM32_UART4_NUMBER, STM32_SERIAL_UART4_PRIORITY); } #endif #if STM32_SERIAL_USE_UART5 if (&SD5 == sdp) { rccEnableUART5(FALSE); nvicEnableVector(STM32_UART5_NUMBER, STM32_SERIAL_UART5_PRIORITY); } #endif #if STM32_SERIAL_USE_USART6 if (&SD6 == sdp) { rccEnableUSART6(FALSE); nvicEnableVector(STM32_USART6_NUMBER, STM32_SERIAL_USART6_PRIORITY); } #endif #if STM32_SERIAL_USE_UART7 if (&SD7 == sdp) { rccEnableUART7(FALSE); nvicEnableVector(STM32_UART7_NUMBER, STM32_SERIAL_UART7_PRIORITY); } #endif #if STM32_SERIAL_USE_UART8 if (&SD8 == sdp) { rccEnableUART8(FALSE); nvicEnableVector(STM32_UART8_NUMBER, STM32_SERIAL_UART8_PRIORITY); } #endif } usart_init(sdp, config); }
/** * @brief Low level serial driver configuration and (re)start. * * @param[in] sdp pointer to a @p SerialDriver object * @param[in] config the architecture-dependent serial driver configuration. * If this parameter is set to @p NULL then a default * configuration is used. * * @notapi */ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { if (config == NULL) config = &default_config; if (sdp->state == SD_STOP) { #if STM32_SERIAL_USE_USART1 if (&SD1 == sdp) { rccEnableUSART1(FALSE); } #endif #if STM32_SERIAL_USE_USART2 if (&SD2 == sdp) { rccEnableUSART2(FALSE); } #endif #if STM32_SERIAL_USE_USART3 if (&SD3 == sdp) { rccEnableUSART3(FALSE); } #endif #if STM32_SERIAL_USE_UART4 if (&SD4 == sdp) { rccEnableUART4(FALSE); } #endif #if STM32_SERIAL_USE_UART5 if (&SD5 == sdp) { rccEnableUART5(FALSE); } #endif #if STM32_SERIAL_USE_USART6 if (&SD6 == sdp) { rccEnableUSART6(FALSE); } #endif #if STM32_SERIAL_USE_UART7 if (&SD7 == sdp) { rccEnableUART7(FALSE); } #endif #if STM32_SERIAL_USE_UART8 if (&SD8 == sdp) { rccEnableUART8(FALSE); } #endif #if STM32_SERIAL_USE_LPUART1 if (&LPSD1 == sdp) { rccEnableLPUART1(FALSE); } #endif } usart_init(sdp, config); }
void usart_support_init(void) { SD1.usart = USART1; SD1.tx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART1_TX_DMA_STREAM); dmaStreamAllocate(SD1.tx.dma, STM32_SERIAL_USART1_PRIORITY, (stm32_dmaisr_t)usart_tx_dma_isr, &SD1.tx); SD1.rx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART1_RX_DMA_STREAM); dmaStreamAllocate(SD1.rx.dma, STM32_SERIAL_USART1_PRIORITY, (stm32_dmaisr_t)usart_rx_dma_isr, &SD1.rx); SD1.dmamode = STM32_DMA_CR_CHSEL(USART1_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SERIAL_USART1_DMA_PRIORITY); usart_support_init_tx(&SD1); usart_support_init_rx(&SD1); rccEnableUSART1(FALSE); SD3.usart = USART3; SD3.tx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART3_TX_DMA_STREAM); dmaStreamAllocate(SD3.tx.dma, STM32_SERIAL_USART3_PRIORITY, (stm32_dmaisr_t)usart_tx_dma_isr, &SD3.tx); SD3.rx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART3_RX_DMA_STREAM); dmaStreamAllocate(SD3.rx.dma, STM32_SERIAL_USART3_PRIORITY, (stm32_dmaisr_t)usart_rx_dma_isr, &SD3.rx); SD3.dmamode = STM32_DMA_CR_CHSEL(USART3_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SERIAL_USART3_DMA_PRIORITY); usart_support_init_tx(&SD3); usart_support_init_rx(&SD3); rccEnableUSART3(FALSE); SD6.usart = USART6; SD6.tx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART6_TX_DMA_STREAM); dmaStreamAllocate(SD6.tx.dma, STM32_SERIAL_USART6_PRIORITY, (stm32_dmaisr_t)usart_tx_dma_isr, &SD6.tx); SD6.rx.dma = STM32_DMA_STREAM(STM32_SERIAL_USART6_RX_DMA_STREAM); dmaStreamAllocate(SD6.rx.dma, STM32_SERIAL_USART6_PRIORITY, (stm32_dmaisr_t)usart_rx_dma_isr, &SD6.rx); SD6.dmamode = STM32_DMA_CR_CHSEL(USART6_TX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_SERIAL_USART6_DMA_PRIORITY); usart_support_init_tx(&SD6); usart_support_init_rx(&SD6); rccEnableUSART6(FALSE); }
/** * @brief Configures and activates the UART peripheral. * * @param[in] uartp pointer to the @p UARTDriver object * * @notapi */ void uart_lld_start(UARTDriver *uartp) { if (uartp->state == UART_STOP) { #if STM32_UART_USE_USART1 if (&UARTD1 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART1_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART1_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUSART1(FALSE); nvicEnableVector(STM32_USART1_NUMBER, STM32_UART_USART1_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART2 if (&UARTD2 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUSART2(FALSE); nvicEnableVector(STM32_USART2_NUMBER, STM32_UART_USART2_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART3 if (&UARTD3 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART3_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART3_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUSART3(FALSE); nvicEnableVector(STM32_USART3_NUMBER, STM32_UART_USART3_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); } #endif #if STM32_UART_USE_UART4 if (&UARTD4 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_UART4_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_UART4_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUART4(FALSE); nvicEnableVector(STM32_UART4_NUMBER, STM32_UART_UART4_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART4_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART4_DMA_PRIORITY); } #endif #if STM32_UART_USE_UART5 if (&UARTD5 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_UART5_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_UART5_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUART5(FALSE); nvicEnableVector(STM32_UART5_NUMBER, STM32_UART_UART5_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART5_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART5_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART6 if (&UARTD6 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART6_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART6_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUSART6(FALSE); nvicEnableVector(STM32_USART6_NUMBER, STM32_UART_USART6_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); } #endif #if STM32_UART_USE_UART7 if (&UARTD7 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_UART7_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_UART7_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUART7(FALSE); nvicEnableVector(STM32_UART7_NUMBER, STM32_UART_UART7_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART7_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART7_DMA_PRIORITY); } #endif #if STM32_UART_USE_UART8 if (&UARTD8 == uartp) { bool b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_UART8_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_UART8_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); osalDbgAssert(!b, "stream already allocated"); rccEnableUART8(FALSE); nvicEnableVector(STM32_UART8_NUMBER, STM32_UART_UART8_IRQ_PRIORITY); uartp->dmamode |= STM32_DMA_CR_CHSEL(UART8_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_UART8_DMA_PRIORITY); } #endif /* Static DMA setup, the transfer size depends on the USART settings, it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->RDR); dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->TDR); uartp->rxbuf = 0; } uartp->rxstate = UART_RX_IDLE; uartp->txstate = UART_TX_IDLE; usart_start(uartp); }
/** * @brief Configures and activates the UART peripheral. * * @param[in] uartp pointer to the @p UARTDriver object * * @notapi */ void uart_lld_start(UARTDriver *uartp) { uartp->dmamode = STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE; if (uartp->state == UART_STOP) { #if STM32_UART_USE_USART1 if (&UARTD1 == uartp) { bool_t b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART1_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #1", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART1_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #2", "stream already allocated"); rccEnableUSART1(FALSE); nvicEnableVector(STM32_USART1_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_USART1_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART1_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART1_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART2 if (&UARTD2 == uartp) { bool_t b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #3", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART2_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #4", "stream already allocated"); rccEnableUSART2(FALSE); nvicEnableVector(STM32_USART2_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_USART2_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART2_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART2_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART3 if (&UARTD3 == uartp) { bool_t b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART3_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART3_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); rccEnableUSART3(FALSE); nvicEnableVector(STM32_USART3_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_USART3_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART3_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART3_DMA_PRIORITY); } #endif #if STM32_UART_USE_USART6 if (&UARTD6 == uartp) { bool_t b; b = dmaStreamAllocate(uartp->dmarx, STM32_UART_USART6_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_rx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #5", "stream already allocated"); b = dmaStreamAllocate(uartp->dmatx, STM32_UART_USART6_IRQ_PRIORITY, (stm32_dmaisr_t)uart_lld_serve_tx_end_irq, (void *)uartp); chDbgAssert(!b, "uart_lld_start(), #6", "stream already allocated"); rccEnableUSART6(FALSE); nvicEnableVector(STM32_USART6_NUMBER, CORTEX_PRIORITY_MASK(STM32_UART_USART6_IRQ_PRIORITY)); uartp->dmamode |= STM32_DMA_CR_CHSEL(USART6_RX_DMA_CHANNEL) | STM32_DMA_CR_PL(STM32_UART_USART6_DMA_PRIORITY); } #endif /* Static DMA setup, the transfer size depends on the USART settings, it is 16 bits if M=1 and PCE=0 else it is 8 bits.*/ if ((uartp->config->cr1 & (USART_CR1_M | USART_CR1_PCE)) == USART_CR1_M) uartp->dmamode |= STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; dmaStreamSetPeripheral(uartp->dmarx, &uartp->usart->DR); dmaStreamSetPeripheral(uartp->dmatx, &uartp->usart->DR); uartp->rxbuf = 0; } uartp->rxstate = UART_RX_IDLE; uartp->txstate = UART_TX_IDLE; usart_start(uartp); }