/* * Free running ms timer. */ static void setup_button_press_timer(void) { rcc_periph_reset_pulse(TIMER_BUTTON_PRESS_RST); timer_set_prescaler(TIMER_BUTTON_PRESS, 3999); /* 4Mhz/1000hz - 1 */ timer_set_period(TIMER_BUTTON_PRESS, 0xffff); timer_enable_counter(TIMER_BUTTON_PRESS); }
void ll_init() { rcc_clock_setup_in_hsi_out_48mhz(); // Initialize used GPIOs and enable peripheral clocks rcc_periph_clock_enable(RCC_GPIOA); rcc_periph_clock_enable(RCC_GPIOC); rcc_periph_clock_enable(RCC_GPIOF); rcc_periph_reset_pulse(RST_GPIOA); rcc_periph_reset_pulse(RST_GPIOC); rcc_periph_reset_pulse(RST_GPIOF); // Pin configuration gpio_mode_setup(GPIOA, GPIO_MODE_INPUT, GPIO_PUPD_NONE, USER_BUTTON); gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, LED0 | LED1); gpio_mode_setup(GPIOC, GPIO_MODE_INPUT, GPIO_PUPD_NONE, CC3000_IRQ); gpio_mode_setup(GPIOC, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, CC3000_DOUT|CC3000_CLK|CC3000_EN); gpio_mode_setup(GPIOF, GPIO_MODE_INPUT, GPIO_PUPD_NONE, CC3000_DIN); gpio_set(GPIOF, CC3000_CS); gpio_mode_setup(GPIOF, GPIO_MODE_OUTPUT, GPIO_PUPD_NONE, CC3000_CS); // Enable EXTI0 IRQ on user pin exti_select_source(EXTI0, GPIOA); exti_set_trigger(EXTI0, EXTI_TRIGGER_RISING); exti_enable_request(EXTI0); // clear counter so it starts right away STK_CVR=0; // Set processor clock for systick // this does it, the systick_set_clocksource doesn't seem to do the // right thing. STK_CSR|=4; // 8MHZ clock -> systick every 1ms systick_set_reload(8000); systick_counter_enable(); }
/* Disable and reset the SPI peripheral using the procedure outlined in the * STM32F302 Reference Manual (section 28.5.8 pg. 815) without blocking. * This function assumes that a transaction isn't currently in progress. */ static void disable_and_reset_spi_properly(void){ dma_disable_channel(DMA1, DMA_CHANNEL3); dma_disable_channel(DMA1, DMA_CHANNEL2); spi_disable(SPI3); rcc_periph_reset_pulse(RST_SPI3); DmaCleanupNeeded = false; TxSpi = false; }
void disconnect_usb(void) { /* Disconnect USB cable by resetting USB Device and pulling USB_DP low*/ rcc_periph_reset_pulse(RST_USB); rcc_periph_clock_enable(RCC_USB); rcc_periph_clock_enable(RCC_GPIOA); gpio_clear(GPIOA, GPIO12); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO12); }
void i2c_reset(uint32_t i2c) { switch (i2c) { case I2C1: rcc_periph_reset_pulse(RST_I2C1); break; #if defined(I2C2_BASE) case I2C2: rcc_periph_reset_pulse(RST_I2C2); break; #endif #if defined(I2C3_BASE) case I2C3: rcc_periph_reset_pulse(RST_I2C3); break; #endif default: break; } }
void i2c1_hw_init(void) { i2c1.reg_addr = (void *)I2C1; i2c1.init_struct = NULL; i2c1.errors = &i2c1_errors; i2c1.watchdog = -1; /* zeros error counter */ ZEROS_ERR_COUNTER(i2c1_errors); // Extra #ifdef I2C_DEBUG_LED LED_INIT(); #else /* reset peripheral to default state ( sometimes not achieved on reset :( ) */ //rcc_periph_reset_pulse(RST_I2C1); /* Configure and enable I2C1 event interrupt --------------------------------*/ nvic_set_priority(NVIC_I2C1_EV_IRQ, NVIC_I2C1_IRQ_PRIO); nvic_enable_irq(NVIC_I2C1_EV_IRQ); /* Configure and enable I2C1 err interrupt ----------------------------------*/ nvic_set_priority(NVIC_I2C1_ER_IRQ, NVIC_I2C1_IRQ_PRIO+1); nvic_enable_irq(NVIC_I2C1_ER_IRQ); /* Enable peripheral clocks -------------------------------------------------*/ /* Enable I2C1 clock */ rcc_periph_clock_enable(RCC_I2C1); /* setup gpio clock and pins */ i2c_setup_gpio(I2C1); rcc_periph_reset_pulse(RST_I2C1); // enable peripheral i2c_peripheral_enable(I2C1); /* * XXX: there is a function to do that already in libopencm3 but I am not * sure if it is correct, using direct register instead (esden) */ //i2c_set_own_7bit_slave_address(I2C1, 0); I2C_OAR1(I2C1) = 0 | 0x4000; // enable error interrupts i2c_enable_interrupt(I2C1, I2C_CR2_ITERREN); i2c_setbitrate(&i2c1, I2C1_CLOCK_SPEED); #endif }
void platform_request_boot(void) { /* Disconnect USB cable by resetting USB Device and pulling USB_DP low*/ rcc_periph_reset_pulse(RST_USB); rcc_periph_clock_enable(RCC_USB); rcc_periph_clock_enable(RCC_GPIOA); gpio_clear(GPIOA, GPIO12); gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_2_MHZ, GPIO_CNF_OUTPUT_OPENDRAIN, GPIO12); /* Assert bootloader pin */ uint32_t crl = GPIOA_CRL; rcc_periph_clock_enable(RCC_GPIOA); /* Enable Pull on GPIOA1. We don't rely on the external pin * really pulled, but only on the value of the CNF register * changed from the reset value */ crl &= 0xffffff0f; crl |= 0x80; GPIOA_CRL = crl; }
/*--------------------------------------------------------------------*/ static void timer_setup(void) { /* Enable TIM2 clock. */ rcc_periph_clock_enable(RCC_TIM2); rcc_periph_reset_pulse(RST_TIM2); /* Timer global mode: - No divider, Alignment edge, Direction up */ timer_set_mode(TIM2, TIM_CR1_CKD_CK_INT, TIM_CR1_CMS_EDGE, TIM_CR1_DIR_UP); timer_continuous_mode(TIM2); timer_set_period(TIM2, PERIOD); timer_disable_oc_output(TIM2, TIM_OC2 | TIM_OC3 | TIM_OC4); timer_enable_oc_output(TIM2, TIM_OC1); timer_disable_oc_clear(TIM2, TIM_OC1); timer_disable_oc_preload(TIM2, TIM_OC1); timer_set_oc_slow_mode(TIM2, TIM_OC1); timer_set_oc_mode(TIM2, TIM_OC1, TIM_OCM_TOGGLE); timer_set_oc_value(TIM2, TIM_OC1, 500); timer_disable_preload(TIM2); /* Set the timer trigger output (for the DAC) to the channel 1 output compare */ timer_set_master_mode(TIM2, TIM_CR2_MMS_COMPARE_OC1REF); timer_enable_counter(TIM2); }
void spi_reset(uint32_t spi_peripheral) { switch (spi_peripheral) { #if defined(SPI1_BASE) case SPI1_BASE: rcc_periph_reset_pulse(RST_SPI1); break; #endif #if defined(SPI2_BASE) case SPI2_BASE: rcc_periph_reset_pulse(RST_SPI2); break; #endif #if defined(SPI3_BASE) case SPI3_BASE: rcc_periph_reset_pulse(RST_SPI3); break; #endif #if defined(SPI4_BASE) case SPI4_BASE: rcc_periph_reset_pulse(RST_SPI4); break; #endif #if defined(SPI5_BASE) case SPI5_BASE: rcc_periph_reset_pulse(RST_SPI5); break; #endif #if defined(SPI6_BASE) case SPI6_BASE: rcc_periph_reset_pulse(RST_SPI6); break; #endif default: break; } }