static int RDMAInit(DISP_MODULE_ENUM module,void * handle)
{
unsigned int idx = rdma_index(module);
ddp_enable_module_clock(module);
DDPMSG("RDMA%dInit CG 0x%x \n",idx, DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0));
return 0;
}
static int RDMADeInit(DISP_MODULE_ENUM module,void * handle)
{
unsigned int idx = rdma_index(module);
DDPMSG("RDMA%dDeinit\n",idx);
ddp_disable_module_clock(module);
return 0;
}
int rdma_reset(DISP_MODULE_ENUM module,void * handle) {
unsigned int delay_cnt=0;
int ret =0;
unsigned int idx = rdma_index(module);
ASSERT(idx <= 2);
DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_SOFT_RESET, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, 1);
while((DISP_REG_GET(idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON)&0x700)==0x100)
{
delay_cnt++;
udelay(10);
if(delay_cnt>10000)
{
ret = -1;
DDPERR("rdma%d_reset timeout, stage 1! DISP_REG_RDMA_GLOBAL_CON=0x%x \n", idx, DISP_REG_GET(idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON));
break;
}
}
DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_SOFT_RESET, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, 0);
delay_cnt =0;
while((DISP_REG_GET(idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON)&0x700)!=0x100)
{
delay_cnt++;
udelay(10);
if(delay_cnt>10000)
{
ret = -1;
DDPERR("rdma%d_reset timeout, stage 2! DISP_REG_RDMA_GLOBAL_CON=0x%x \n", idx, DISP_REG_GET(idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON));
break;
}
}
return ret;
}
static int RDMAPollingInterrupt(DISP_MODULE_ENUM module, int bit, int timeout)
{
unsigned int idx = rdma_index(module);
unsigned int cnt = 0;
unsigned int regval = 0;
if( timeout <= 0)
{
while((DISP_REG_GET(idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS) & bit)==0);
cnt = 1;
}
else
{
// time need to update
cnt = timeout*1000/100;
while(cnt > 0)
{
cnt--;
regval = DISP_REG_GET(idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS);
if(regval & bit )
{
DISP_CPU_REG_SET(idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS, ~regval);
break;
}
udelay(100);
}
}
//should clear?
DDPMSG(" RDMA%d polling interrupt ret =%d \n", idx, cnt);
return cnt;
}
void rdma_dump_reg(DISP_MODULE_ENUM module)
{
unsigned int idx = rdma_index(module);
DDPDUMP("== DISP RDMA%d REGS ==\n", idx);
DDPDUMP("(0x000)R_INTEN =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_INT_ENABLE+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x004)R_INTS =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_INT_STATUS+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x010)R_CON =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x014)R_SIZE0 =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x018)R_SIZE1 =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x01c)R_TAR_LINE =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_TARGET_LINE+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x024)R_M_CON =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_CON+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0xf00)R_M_S_ADDR =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x02c)R_M_SRC_PITCH =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_SRC_PITCH+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x030)R_M_GMC_SET0 =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x034)R_M_SLOW_CON =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_SLOW_CON+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x038)R_M_GMC_SET1 =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x040)R_FIFO_CON =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_FIFO_CON+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x044)R_FIFO_LOG =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_FIFO_LOG+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x078)R_PRE_ADD0 =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_PRE_ADD_0+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x07c)R_PRE_ADD1 =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_PRE_ADD_1+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x080)R_PRE_ADD2 =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_PRE_ADD_2+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x084)R_POST_ADD0 =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_POST_ADD_0+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x088)R_POST_ADD1 =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_POST_ADD_1+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x08c)R_POST_ADD2 =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_POST_ADD_2+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x090)R_DUMMY =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_DUMMY+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x094)R_OUT_SEL =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_DEBUG_OUT_SEL+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x094)R_M_START =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x0f0)R_IN_PXL_CNT =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_IN_P_CNT+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x0f4)R_IN_LINE_CNT =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_IN_LINE_CNT+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x0f8)R_OUT_PXL_CNT =0x%x\n", DISP_REG_GET(DISP_REG_RDMA_OUT_P_CNT+DISP_RDMA_INDEX_OFFSET*idx));
DDPDUMP("(0x0fc)R_OUT_LINE_CNT=0x%x\n", DISP_REG_GET(DISP_REG_RDMA_OUT_LINE_CNT+DISP_RDMA_INDEX_OFFSET*idx));
return;
}
void rdma_dump_analysis(DISP_MODULE_ENUM module)
{
unsigned int idx = rdma_index(module);
DDPDUMP("==DISP RDMA%d ANALYSIS==\n", idx);
DDPDUMP("rdma%d: en=%d, memory mode=%d, w=%d, h=%d, pitch=%d, addr=0x%x, fmt=%s, fifo_min=%d, \
in_p_cnt=%d, in_l_cnt=%d, out_p_cnt=%d, out_l_cnt=%d, rdma_start_time=%lld ns,rdma_end_time=%lld ns\n",
idx,
DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_RDMA_INDEX_OFFSET*idx)&0x1,
(DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_RDMA_INDEX_OFFSET*idx)&0x2)?1:0,
DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0+DISP_RDMA_INDEX_OFFSET*idx)&0xfff,
DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1+DISP_RDMA_INDEX_OFFSET*idx)&0xfffff,
DISP_REG_GET(DISP_REG_RDMA_MEM_SRC_PITCH+DISP_RDMA_INDEX_OFFSET*idx),
DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR+DISP_RDMA_INDEX_OFFSET*idx),
rdma_intput_format_name(
(DISP_REG_GET(DISP_REG_RDMA_MEM_CON+DISP_RDMA_INDEX_OFFSET*idx)>>4)&0xf,
(DISP_REG_GET(DISP_REG_RDMA_MEM_CON+DISP_RDMA_INDEX_OFFSET*idx)>>8)&0x1
),
DISP_REG_GET(DISP_REG_RDMA_FIFO_LOG+DISP_RDMA_INDEX_OFFSET*idx),
DISP_REG_GET(DISP_REG_RDMA_IN_P_CNT+DISP_RDMA_INDEX_OFFSET*idx),
DISP_REG_GET(DISP_REG_RDMA_IN_LINE_CNT+DISP_RDMA_INDEX_OFFSET*idx),
DISP_REG_GET(DISP_REG_RDMA_OUT_P_CNT+DISP_RDMA_INDEX_OFFSET*idx),
DISP_REG_GET(DISP_REG_RDMA_OUT_LINE_CNT+DISP_RDMA_INDEX_OFFSET*idx),
rdma_start_time[idx],
rdma_end_time[idx]
);
DDPDUMP("irq cnt: start=%d, end=%d, underflow=%d, targetline=%d \n",
rdma_start_irq_cnt[idx], rdma_done_irq_cnt[idx], rdma_underflow_irq_cnt[idx], rdma_targetline_irq_cnt[idx]);
return ;
}
static int do_rdma_config_l(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* handle)
{
RDMA_CONFIG_STRUCT * r_config = & pConfig->rdma_config;
enum RDMA_MODE mode = rdma_config_mode(r_config->address);
LCM_PARAMS *lcm_param = &(pConfig->dispif_config);
unsigned int width = pConfig->dst_dirty ? pConfig->dst_w : r_config->width;
unsigned int height = pConfig->dst_dirty ? pConfig->dst_h : r_config->height;
if(pConfig->fps)
{
rdma_fps[rdma_index(module)] = pConfig->fps/100;
}
if(mode == RDMA_MODE_DIRECT_LINK &&
r_config->security != DISP_NORMAL_BUFFER) {
DDPERR("%s: rdma directlink BUT is sec ??!!\n", __FUNCTION__);
}
rdma_config(module,
mode,
(mode == RDMA_MODE_DIRECT_LINK) ? 0 : r_config->address, // address
(mode == RDMA_MODE_DIRECT_LINK) ? eRGB888 : r_config->inputFormat, // inputFormat
(mode == RDMA_MODE_DIRECT_LINK) ? 0 : r_config->pitch, // pitch
width,
height,
lcm_param->dsi.ufoe_enable,
r_config->security,
handle);
return 0;
}
int rdma_resolution_test(DISP_MODULE_ENUM module,unsigned int fw,unsigned fh)
{
int ret=0;
unsigned int idx = rdma_index(module);
int pw = DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0+DISP_RDMA_INDEX_OFFSET*idx)&0xfff;
int ph = DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1+DISP_RDMA_INDEX_OFFSET*idx)&0xfffff;
//reset rdma
ret=rdma_reset(module,NULL);
if(ret!=0)
{
printk("reset fail\n");
return -1;
}
DISP_REG_SET_FIELD(NULL,SIZE_CON_0_FLD_OUTPUT_FRAME_WIDTH, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_0, pw);
DISP_REG_SET_FIELD(NULL,SIZE_CON_1_FLD_OUTPUT_FRAME_HEIGHT, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_1, ph);
DISP_REG_SET_FIELD(NULL,SIZE_CON_0_FLD_OUTPUT_FRAME_WIDTH, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_0, fw);
DISP_REG_SET_FIELD(NULL,SIZE_CON_1_FLD_OUTPUT_FRAME_HEIGHT, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_1, fh);
int w = DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0+DISP_RDMA_INDEX_OFFSET*idx)&0xfff;
int h = DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1+DISP_RDMA_INDEX_OFFSET*idx)&0xfffff;
if((w!=pw) && (h!=ph))
{
printk("w=%d,h=%d,pw=%d,ph=%d,fw=%d,fh=%d\n",w,h,pw,ph,fw,fh);
DISP_REG_SET_FIELD(NULL,SIZE_CON_0_FLD_OUTPUT_FRAME_WIDTH, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_0, pw);
DISP_REG_SET_FIELD(NULL,SIZE_CON_1_FLD_OUTPUT_FRAME_HEIGHT, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_1, ph);
ret =-1;
}
return ret;
}
int rdma_stop(DISP_MODULE_ENUM module,void * handle) {
unsigned int idx = rdma_index(module);
ASSERT(idx <= 2);
DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_ENGINE_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, 0);
DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_INT_ENABLE, 0);
DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS, 0);
return 0;
}
static int rdma_deinit(DISP_MODULE_ENUM module,void * handle)
{
unsigned int idx = rdma_index(module);
#ifdef ENABLE_CLK_MGR
disable_clock(MT_CG_DISP0_DISP_RDMA0+idx , "DDP");
#endif
DDPMSG("rdma%d_deinit CG 0x%x \n",idx, DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0));
return 0;
}
static int rdma_config_l(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void* handle)
{
RDMA_CONFIG_STRUCT * r_config = & pConfig->rdma_config;
enum RDMA_MODE mode = r_config->address ? RDMA_MODE_MEMORY : RDMA_MODE_DIRECT_LINK;
LCM_PARAMS *lcm_param = &(pConfig->dispif_config);
if(pConfig->dst_dirty)
{
if(pConfig->fps)
{
rdma_fps[rdma_index(module)] = pConfig->fps/100;
}
//config to direct link mode
rdma_config(module,
mode, //RDMA_MODE_DIRECT_LINK, // link mode
(mode == RDMA_MODE_DIRECT_LINK) ? 0 : r_config->address, // address
(mode == RDMA_MODE_DIRECT_LINK) ? eRGB888 : r_config->inputFormat, // inputFormat
(mode == RDMA_MODE_DIRECT_LINK) ? 0 : r_config->pitch, // pitch
pConfig->dst_w, // width
pConfig->dst_h, // height
lcm_param->dsi.ufoe_enable,
handle);
}
else if(pConfig->rdma_dirty)
{
if(pConfig->fps)
{
rdma_fps[rdma_index(module)] = pConfig->fps/100;
}
// decouple mode may use
rdma_config(module,
mode, // link mode
(mode == RDMA_MODE_DIRECT_LINK) ? 0 : r_config->address, // address
(mode == RDMA_MODE_DIRECT_LINK) ? eRGB888 : r_config->inputFormat, // inputFormat
(mode == RDMA_MODE_DIRECT_LINK) ? 0 : r_config->pitch, // pitch
r_config->width, // width
r_config->height, // height
lcm_param->dsi.ufoe_enable,
handle);
}
return 0;
}
static int setup_rdma_sec(DISP_MODULE_ENUM module, disp_ddp_path_config* pConfig, void *handle)
{
static int rdma_is_sec[2];
CMDQ_ENG_ENUM cmdq_engine;
int rdma_idx = rdma_index(module);
DISP_BUFFER_TYPE security = pConfig->rdma_config.security;
enum RDMA_MODE mode = rdma_config_mode(pConfig->rdma_config.address);
cmdq_engine = rdma_idx==0 ? CMDQ_ENG_DISP_RDMA0 : CMDQ_ENG_DISP_RDMA1;
if(!handle) {
DDPMSG("[SVP] bypass rdma sec setting sec=%d,handle=NULL\n", security);
return 0;
}
/* sec setting make sence only in memory mode ! */
if(mode == RDMA_MODE_MEMORY) {
if(security == DISP_SECURE_BUFFER) {
cmdqRecSetSecure(handle, 1);
/* set engine as sec */
cmdqRecSecureEnablePortSecurity(handle, (1LL << cmdq_engine));
//cmdqRecSecureEnableDAPC(handle, (1LL << cmdq_engine));
if(rdma_is_sec[rdma_idx] == 0)
DDPMSG("[SVP] switch rdma%d to sec\n", rdma_idx);
rdma_is_sec[rdma_idx] = 1;
} else {
if(rdma_is_sec[rdma_idx]) {
/* rdma is in sec stat, we need to switch it to nonsec */
cmdqRecHandle nonsec_switch_handle;
int ret;
ret = cmdqRecCreate(CMDQ_SCENARIO_DISP_PRIMARY_DISABLE_SECURE_PATH, &(nonsec_switch_handle));
if(ret)
DDPAEE("[SVP]fail to create disable handle %s ret=%d\n", __FUNCTION__, ret);
cmdqRecReset(nonsec_switch_handle);
_cmdq_insert_wait_frame_done_token_mira(nonsec_switch_handle);
cmdqRecSetSecure(nonsec_switch_handle, 1);
/*ugly work around by kzhang !!. will remove when cmdq delete disable scenario.
* To avoid translation fault like ovl (see notes in ovl.c)*/
do_rdma_config_l(module, pConfig, nonsec_switch_handle);
/*in fact, dapc/port_sec will be disabled by cmdq*/
cmdqRecSecureEnablePortSecurity(nonsec_switch_handle, (1LL << cmdq_engine));
//cmdqRecSecureEnableDAPC(nonsec_switch_handle, (1LL << cmdq_engine));
cmdqRecFlush(nonsec_switch_handle);
cmdqRecDestroy(nonsec_switch_handle);
DDPMSG("[SVP] switch rdma%d to nonsec done\n", rdma_idx);
}
rdma_is_sec[rdma_idx] = 0;
}
}
return 0;
}
static int rdma_clock_off(DISP_MODULE_ENUM module,void * handle)
{
unsigned int idx = rdma_index(module);
#ifdef ENABLE_CLK_MGR
if (idx == 0) {
disable_clock(MT_CG_DISP0_DISP_RDMA0, "RDMA0");
}else{
disable_clock(MT_CG_DISP0_DISP_RDMA1, "RDMA1");
}
#endif
DDPMSG("rdma_%d_clock_off CG 0x%x \n",idx, DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0));
return 0;
}
static int rdma_clock_off(DISP_MODULE_ENUM module,void * handle)
{
unsigned int idx = rdma_index(module);
if(idx == 0){
disable_clock(MT_CG_DISP0_DISP_RDMA0 , "rdma0");
}else if(idx == 1){
disable_clock(MT_CG_DISP0_DISP_RDMA1 , "rdma1");
} else if(idx == 2){
disable_clock(MT_CG_DISP0_DISP_RDMA2 , "rdma2");
}
DDPMSG("rdma_%d_clock_off CG 0x%x \n",idx, DISP_REG_GET(DISP_REG_CONFIG_MMSYS_CG_CON0));
return 0;
}
int RDMAWait(DISP_MODULE_ENUM module,void * handle)
{
unsigned int cnt = 0;
unsigned int idx = rdma_index(module);
// polling interrupt status
while((DISP_REG_GET(idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS) & 0x4) != 0x4)
{
cnt++;
if(cnt>1000)
{
DDPERR("RDMA%dWait timeout! \n", idx);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS , 0x0);
return -1;
}
}
DDPMSG(" RDMA%dWait cnt=%d \n", idx, cnt);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_STATUS , 0x0);
return 0;
}
void rdma_dump_reg(DISP_MODULE_ENUM module)
{
unsigned int idx = rdma_index(module);
unsigned int off_st = DISP_RDMA_INDEX_OFFSET*idx;
DDPDUMP("== DISP RDMA%d REGS ==\n", idx);
DDPDUMP("RDMA:0x000=0x%08x,0x004=0x%08x,0x010=0x%08x,0x014=0x%08x\n",
DISP_REG_GET(DISP_REG_RDMA_INT_ENABLE + off_st),
DISP_REG_GET(DISP_REG_RDMA_INT_STATUS + off_st),
DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON + off_st),
DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0 + off_st));
DDPDUMP("RDMA:0x018=0x%08x,0x01c=0x%08x,0x024=0x%08x,0xf00=0x%08x\n",
DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1 + off_st),
DISP_REG_GET(DISP_REG_RDMA_TARGET_LINE + off_st),
DISP_REG_GET(DISP_REG_RDMA_MEM_CON + off_st),
DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR + off_st));
DDPDUMP("RDMA:0x02c=0x%08x,0x030=0x%08x,0x034=0x%08x,0x038=0x%08x\n",
DISP_REG_GET(DISP_REG_RDMA_MEM_SRC_PITCH + off_st),
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_0 + off_st),
DISP_REG_GET(DISP_REG_RDMA_MEM_SLOW_CON + off_st),
DISP_REG_GET(DISP_REG_RDMA_MEM_GMC_SETTING_1 + off_st));
DDPDUMP("RDMA:0x040=0x%08x,0x044=0x%08x,0x078=0x%08x,0x07c=0x%08x\n",
DISP_REG_GET(DISP_REG_RDMA_FIFO_CON + off_st),
DISP_REG_GET(DISP_REG_RDMA_FIFO_LOG + off_st),
DISP_REG_GET(DISP_REG_RDMA_PRE_ADD_0 + off_st),
DISP_REG_GET(DISP_REG_RDMA_PRE_ADD_1 + off_st));
DDPDUMP("RDMA:0x080=0x%08x,0x084=0x%08x,0x088=0x%08x,0x08c=0x%08x\n",
DISP_REG_GET(DISP_REG_RDMA_PRE_ADD_2 + off_st),
DISP_REG_GET(DISP_REG_RDMA_POST_ADD_0 + off_st),
DISP_REG_GET(DISP_REG_RDMA_POST_ADD_1 + off_st),
DISP_REG_GET(DISP_REG_RDMA_POST_ADD_2 + off_st));
DDPDUMP("RDMA:0x090=0x%08x,0x094=0x%08x,0x094=0x%08x\n",
DISP_REG_GET(DISP_REG_RDMA_DUMMY + off_st),
DISP_REG_GET(DISP_REG_RDMA_DEBUG_OUT_SEL + off_st),
DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR + off_st));
return;
}
void rdma_dump_analysis(DISP_MODULE_ENUM module)
{
unsigned int idx = rdma_index(module);
DDPDUMP("==DISP RDMA%d ANALYSIS==\n", idx);
DDPDUMP("rdma%d: en=%d, w=%d, h=%d, pitch=%d, addr=0x%x, fmt=%s, fifo_min=%d rdma_start_time=%lld ns,rdma_end_time=%lld ns\n",
idx,
DISP_REG_GET(DISP_REG_RDMA_GLOBAL_CON+DISP_RDMA_INDEX_OFFSET*idx)&0x1,
DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_0+DISP_RDMA_INDEX_OFFSET*idx)&0xfff,
DISP_REG_GET(DISP_REG_RDMA_SIZE_CON_1+DISP_RDMA_INDEX_OFFSET*idx)&0xfffff,
DISP_REG_GET(DISP_REG_RDMA_MEM_SRC_PITCH+DISP_RDMA_INDEX_OFFSET*idx),
DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR+DISP_RDMA_INDEX_OFFSET*idx),
rdma_intput_format_name(
(DISP_REG_GET(DISP_REG_RDMA_MEM_CON+DISP_RDMA_INDEX_OFFSET*idx)>>4)&0xf,
(DISP_REG_GET(DISP_REG_RDMA_MEM_CON+DISP_RDMA_INDEX_OFFSET*idx)>>8)&0x1
),
DISP_REG_GET(DISP_REG_RDMA_FIFO_LOG+DISP_RDMA_INDEX_OFFSET*idx),
rdma_start_time[idx],
rdma_end_time[idx]
);
return ;
}
int rdma_build_cmdq(DISP_MODULE_ENUM module,void *cmdq_trigger_handle, CMDQ_STATE state)
{
int ret = 0;
unsigned int idx = rdma_index(module);
if(cmdq_trigger_handle == NULL)
{
DDPERR("cmdq_trigger_handle is NULL\n");
return -1;
}
if(disp_helper_get_option(DISP_HELPER_OPTION_DYNAMIC_SWITCH_UNDERFLOW_EN))
{
if(state == CMDQ_AFTER_STREAM_EOF)
{
DISP_REG_SET_FIELD(cmdq_trigger_handle,FIFO_CON_FLD_FIFO_UNDERFLOW_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 0);
}
else if(state == CMDQ_AFTER_STREAM_SOF)
{
DISP_REG_SET_FIELD(cmdq_trigger_handle,FIFO_CON_FLD_FIFO_UNDERFLOW_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 1);
}
}
return 0;
}
void rdma_get_address(DISP_MODULE_ENUM module, unsigned long * addr)
{
unsigned int idx = rdma_index(module);
*addr = DISP_REG_GET(DISP_REG_RDMA_MEM_START_ADDR+DISP_RDMA_INDEX_OFFSET*idx);
return ;
}
// fixme: spec has no RDMA format, fix enum definition here
int RDMAConfig(DISP_MODULE_ENUM module,
enum RDMA_MODE mode,
unsigned address,
DpColorFormat inFormat,
unsigned pitch,
unsigned width,
unsigned height,
unsigned ufoe_enable,
void * handle) // ourput setting
{
unsigned int output_is_yuv = 0;
enum RDMA_INPUT_FORMAT inputFormat = rdma_input_format_convert(inFormat);
unsigned int bpp = rdma_input_format_bpp(inputFormat);
unsigned int input_is_yuv = rdma_input_format_color_space(inputFormat);
unsigned int input_swap = rdma_input_format_byte_swap(inputFormat);
unsigned int input_format_reg = rdma_input_format_reg_value(inputFormat);
unsigned int idx = rdma_index(module);
//DDPDBG("RDMAConfig idx %d, mode %d, address 0x%x, inputformat %d, input_swap %u, pitch %u, width %u, height %u\n",
// idx, mode, address, inputFormat,input_swap, pitch,width, height);
ASSERT(idx <= 2);
if((width > RDMA_MAX_WIDTH) || (height > RDMA_MAX_HEIGHT))
{
DDPERR("RDMA input overflow, w=%d, h=%d, max_w=%d, max_h=%d\n", width, height, RDMA_MAX_WIDTH, RDMA_MAX_HEIGHT);
}
if(input_is_yuv==1 && output_is_yuv==0)
{
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_ENABLE, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 1);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_INT_MTX_SEL, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 0x6);
// set color conversion matrix
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C00, coef_rdma_601_y2r[0][0] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C01, coef_rdma_601_y2r[0][1] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C02, coef_rdma_601_y2r[0][2] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C10, coef_rdma_601_y2r[1][0] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C11, coef_rdma_601_y2r[1][1] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C12, coef_rdma_601_y2r[1][2] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C20, coef_rdma_601_y2r[2][0] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C21, coef_rdma_601_y2r[2][1] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C22, coef_rdma_601_y2r[2][2] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_PRE_ADD_0, coef_rdma_601_y2r[3][0]);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_PRE_ADD_1, coef_rdma_601_y2r[3][1]);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_PRE_ADD_2, coef_rdma_601_y2r[3][2]);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_POST_ADD_0, coef_rdma_601_y2r[4][0]);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_POST_ADD_1, coef_rdma_601_y2r[4][1]);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_POST_ADD_2, coef_rdma_601_y2r[4][2]);
}
else if(input_is_yuv==0 && output_is_yuv==1)
{
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_ENABLE, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 1);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_INT_MTX_SEL, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 0x2);
// set color conversion matrix
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C00, coef_rdma_601_r2y[0][0] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C01, coef_rdma_601_r2y[0][1] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C02, coef_rdma_601_r2y[0][2] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C10, coef_rdma_601_r2y[1][0] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C11, coef_rdma_601_r2y[1][1] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C12, coef_rdma_601_r2y[1][2] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C20, coef_rdma_601_r2y[2][0] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C21, coef_rdma_601_r2y[2][1] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_C22, coef_rdma_601_r2y[2][2] );
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_PRE_ADD_0, coef_rdma_601_r2y[3][0]);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_PRE_ADD_1, coef_rdma_601_r2y[3][1]);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_PRE_ADD_2, coef_rdma_601_r2y[3][2]);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_POST_ADD_0, coef_rdma_601_r2y[4][0]);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_POST_ADD_1, coef_rdma_601_r2y[4][1]);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_POST_ADD_2, coef_rdma_601_r2y[4][2]);
}
else
{
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_ENABLE, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 0);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_INT_MTX_SEL, idx * DISP_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 0);
}
DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_MODE_SEL, idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, mode);
// FORMAT & SWAP only works when RDMA memory mode, set both to 0 when RDMA direct link mode.
DISP_REG_SET_FIELD(handle,MEM_CON_FLD_MEM_MODE_INPUT_FORMAT, idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_MEM_CON, ((mode == RDMA_MODE_DIRECT_LINK) ? 0 : input_format_reg&0xf));
DISP_REG_SET_FIELD(handle,MEM_CON_FLD_MEM_MODE_INPUT_SWAP, idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_MEM_CON, ((mode == RDMA_MODE_DIRECT_LINK) ? 0 : input_swap));
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_MEM_START_ADDR, address);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_MEM_SRC_PITCH, pitch);
DISP_REG_SET(handle,idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_INT_ENABLE, 0x1F);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_OUTPUT_FRAME_WIDTH, idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_0, width);
DISP_REG_SET_FIELD(handle,SIZE_CON_1_FLD_OUTPUT_FRAME_HEIGHT, idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_1, height);
rdma_set_ultra(idx, width, height, bpp, 60, handle);
#if 1
if(ufoe_enable==0) //UFOE bypassed, enable RDMA underflow intr, else disable RDMA underflow intr
{
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_FIFO_UNDERFLOW_EN, idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 1);
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_OUTPUT_VALID_FIFO_THRESHOLD, idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 16);
}
else
{
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_FIFO_UNDERFLOW_EN, idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 1);
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_OUTPUT_VALID_FIFO_THRESHOLD, idx*DISP_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, width*3*3/16/2); //FHD:304, HD:203, QHD:151
}
#endif
return 0;
}
void rdma_set_target_line(DISP_MODULE_ENUM module, unsigned int line,void * handle)
{
unsigned int idx = rdma_index(module);
DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_TARGET_LINE, line);
}
static int rdma_config(DISP_MODULE_ENUM module,
enum RDMA_MODE mode,
unsigned long address,
DpColorFormat inFormat,
unsigned pitch,
unsigned width,
unsigned height,
unsigned ufoe_enable,
DISP_BUFFER_TYPE sec,
void * handle)
{
unsigned int output_is_yuv = 0;
enum RDMA_INPUT_FORMAT inputFormat = rdma_input_format_convert(inFormat);
unsigned int bpp = rdma_input_format_bpp(inputFormat);
unsigned int input_is_yuv = rdma_input_format_color_space(inputFormat);
unsigned int input_swap = rdma_input_format_byte_swap(inputFormat);
unsigned int input_format_reg = rdma_input_format_reg_value(inputFormat);
unsigned int color_matrix = 0x4; //0100 MTX_JPEG_TO_RGB (YUV FUll TO RGB)
unsigned int idx = rdma_index(module);
#if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) && defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
DDPMSG("RDMAConfig idx %d, mode %d, address 0x%lx, inputformat %s, pitch %u, width %u, height %u,sec%d\n",
idx, mode, address, rdma_intput_format_name(inputFormat,input_swap), pitch,width, height, sec);
#else
DDPDBG("RDMAConfig idx %d, mode %d, address 0x%lx, inputformat %s, pitch %u, width %u, height %u,sec%d\n",
idx, mode, address, rdma_intput_format_name(inputFormat,input_swap), pitch,width, height, sec);
#endif
ASSERT(idx <= 2);
if((width > RDMA_MAX_WIDTH) || (height > RDMA_MAX_HEIGHT))
{
DDPERR("RDMA input overflow, w=%d, h=%d, max_w=%d, max_h=%d\n", width, height, RDMA_MAX_WIDTH, RDMA_MAX_HEIGHT);
}
if(input_is_yuv==1 && output_is_yuv==0)
{
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_ENABLE, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 1);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_INT_MTX_SEL, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, color_matrix);
}
else if(input_is_yuv==0 && output_is_yuv==1)
{
color_matrix = 0x2; //0x0010, RGB_TO_BT601
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_ENABLE, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 1);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_INT_MTX_SEL, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, color_matrix);
}
else
{
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_ENABLE, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 0);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_INT_MTX_SEL, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 0);
}
DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_MODE_SEL, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, mode);
// FORMAT & SWAP only works when RDMA memory mode, set both to 0 when RDMA direct link mode.
DISP_REG_SET_FIELD(handle,MEM_CON_FLD_MEM_MODE_INPUT_FORMAT, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_CON, ((mode == RDMA_MODE_DIRECT_LINK) ? 0 : input_format_reg&0xf));
DISP_REG_SET_FIELD(handle,MEM_CON_FLD_MEM_MODE_INPUT_SWAP, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_CON, ((mode == RDMA_MODE_DIRECT_LINK) ? 0 : input_swap));
if(sec != DISP_SECURE_BUFFER) {
DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_START_ADDR, address);
} else {
int m4u_port;
unsigned int size = pitch * height;
m4u_port = idx==0 ? M4U_PORT_DISP_RDMA0 : M4U_PORT_DISP_RDMA1;
/* for sec layer, addr variable stores sec handle*/
/* we need to pass this handle and offset to cmdq driver */
/* cmdq sec driver will help to convert handle to correct address */
cmdqRecWriteSecure(handle, disp_addr_convert(idx*DISP_RDMA_INDEX_OFFSET+DISP_REG_RDMA_MEM_START_ADDR),
CMDQ_SAM_H_2_MVA, address, 0, size, m4u_port);
//DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+DISP_REG_RDMA_MEM_START_ADDR, address-0xbc000000+0x8c00000);
}
DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_SRC_PITCH, pitch);
//DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_INT_ENABLE, 0x3F);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_OUTPUT_FRAME_WIDTH, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_0, width);
DISP_REG_SET_FIELD(handle,SIZE_CON_1_FLD_OUTPUT_FRAME_HEIGHT, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_1, height);
rdma_set_ultra(idx, width, height, bpp, rdma_fps[idx], handle);
#if 1
if(0) //UFOE bypassed, enable RDMA underflow intr, else disable RDMA underflow intr
{
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_FIFO_UNDERFLOW_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 1);
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_OUTPUT_VALID_FIFO_THRESHOLD, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, gRDMAFIFOLen);
}
else
{
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_FIFO_UNDERFLOW_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 1);
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_OUTPUT_VALID_FIFO_THRESHOLD, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, width*3*3/16/2); //FHD:304, HD:203, QHD:151
}
#endif
return 0;
}
// fixme: spec has no RDMA format, fix enum definition here
int rdma_config(DISP_MODULE_ENUM module,
enum RDMA_MODE mode,
unsigned long address,
DpColorFormat inFormat,
unsigned pitch,
unsigned width,
unsigned height,
unsigned ufoe_enable,
void * handle) // ourput setting
{
unsigned int output_is_yuv = 0;
enum RDMA_INPUT_FORMAT inputFormat = rdma_input_format_convert(inFormat);
unsigned int bpp = rdma_input_format_bpp(inputFormat);
unsigned int input_is_yuv = rdma_input_format_color_space(inputFormat);
unsigned int input_swap = rdma_input_format_byte_swap(inputFormat);
unsigned int input_format_reg = rdma_input_format_reg_value(inputFormat);
unsigned int color_matrix = 0x4; //0100 MTX_JPEG_TO_RGB (YUV FUll TO RGB)
unsigned int idx = rdma_index(module);
DDPDBG("RDMAConfig idx %d, mode %d, address 0x%x, inputformat %s, pitch %u, width %u, height %u\n",
idx, mode, address, rdma_intput_format_name(inputFormat,input_swap), pitch,width, height);
ASSERT(idx <= 2);
if((width > RDMA_MAX_WIDTH) || (height > RDMA_MAX_HEIGHT))
{
DDPERR("RDMA input overflow, w=%d, h=%d, max_w=%d, max_h=%d\n", width, height, RDMA_MAX_WIDTH, RDMA_MAX_HEIGHT);
}
if(input_is_yuv==1 && output_is_yuv==0)
{
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_ENABLE, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 1);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_INT_MTX_SEL, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, color_matrix);
}
else if(input_is_yuv==0 && output_is_yuv==1)
{
color_matrix = 0x2; //0x0010, RGB_TO_BT601
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_ENABLE, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 1);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_INT_MTX_SEL, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, color_matrix);
}
else
{
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_ENABLE, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 0);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_MATRIX_INT_MTX_SEL, idx * DISP_RDMA_INDEX_OFFSET + DISP_REG_RDMA_SIZE_CON_0, 0);
}
DISP_REG_SET_FIELD(handle,GLOBAL_CON_FLD_MODE_SEL, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_GLOBAL_CON, mode);
// FORMAT & SWAP only works when RDMA memory mode, set both to 0 when RDMA direct link mode.
DISP_REG_SET_FIELD(handle,MEM_CON_FLD_MEM_MODE_INPUT_FORMAT, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_CON, ((mode == RDMA_MODE_DIRECT_LINK) ? 0 : input_format_reg&0xf));
DISP_REG_SET_FIELD(handle,MEM_CON_FLD_MEM_MODE_INPUT_SWAP, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_CON, ((mode == RDMA_MODE_DIRECT_LINK) ? 0 : input_swap));
DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_START_ADDR, address);
DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_MEM_SRC_PITCH, pitch);
DISP_REG_SET(handle,idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_INT_ENABLE, 0x3F);
DISP_REG_SET_FIELD(handle,SIZE_CON_0_FLD_OUTPUT_FRAME_WIDTH, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_0, width);
DISP_REG_SET_FIELD(handle,SIZE_CON_1_FLD_OUTPUT_FRAME_HEIGHT, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_SIZE_CON_1, height);
rdma_set_ultra(idx, width, height, bpp, rdma_fps[idx], handle);
#if 1
if(ufoe_enable==0) //UFOE bypassed, enable RDMA underflow intr, else disable RDMA underflow intr
{
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_FIFO_UNDERFLOW_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 1);
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_OUTPUT_VALID_FIFO_THRESHOLD, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 16);
}
else
{
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_FIFO_UNDERFLOW_EN, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, 1);
DISP_REG_SET_FIELD(handle,FIFO_CON_FLD_OUTPUT_VALID_FIFO_THRESHOLD, idx*DISP_RDMA_INDEX_OFFSET+ DISP_REG_RDMA_FIFO_CON, width*3*3/16/2); //FHD:304, HD:203, QHD:151
}
#endif
return 0;
}