/** Generate bytes using the Intel RDRAND instruction. */
static int
ottery_get_entropy_rdrand(const struct ottery_entropy_config *cfg,
struct ottery_entropy_state *state,
uint8_t *out, size_t outlen)
{
int err;
uint32_t *up = (uint32_t *) out;
(void) cfg;
(void) state;
if (! (ottery_get_cpu_capabilities_() & OTTERY_CPUCAP_RAND) || ottery_valgrind_)
return OTTERY_ERR_INIT_STRONG_RNG;
while (outlen >= 4) {
if ((err = rdrand(up)))
return err;
up += 1;
outlen -= 4;
}
if (outlen) {
uint32_t tmp;
if ((err = rdrand(&tmp)))
return err;
memcpy(up, &tmp, outlen);
}
return 0;
}
static inline void
rdrandom_buf(void *b, size_t n)
{
unsigned *cp = b;
unsigned i;
for (i = 0; i < n/sizeof(unsigned); ++i) {
*cp++ = rdrand();
}
}
/*
* Determine i/o configuration for a machine.
*/
void
cpu_configure(void)
{
#if NBIOS32 > 0
bios32_init();
#endif
x86_64_proc0_tss_ldt_init();
if (config_rootfound("mainbus", NULL) == NULL)
panic("configure: mainbus not configured");
intr_printconfig();
#if NIOAPIC > 0
lapic_set_lvt();
ioapic_enable();
#endif
#ifdef MULTIPROCESSOR
cpu_init_idle_pcbs();
#endif
lcr8(0);
spl0();
cold = 0;
/*
* At this point the RNG is running, and if FSXR is set we can
* use it. Here we setup a periodic timeout to collect the data.
*/
if (viac3_rnd_present) {
timeout_set(&viac3_rnd_tmo, viac3_rnd, &viac3_rnd_tmo);
viac3_rnd(&viac3_rnd_tmo);
}
if (has_rdrand) {
timeout_set(&rdrand_tmo, rdrand, &rdrand_tmo);
rdrand(&rdrand_tmo);
}
#ifdef CRYPTO
/*
* Also, if the chip has crypto available, enable it.
*/
if (amd64_has_xcrypt)
viac3_crypto_setup();
if (amd64_has_aesni)
aesni_setup();
#endif
}
int
cpu_activate(struct device *self, int act)
{
struct cpu_info *sc = (struct cpu_info *)self;
switch (act) {
case DVACT_RESUME:
if (sc->ci_cpuid == 0)
rdrand(NULL);
break;
}
return (0);
}
void stress(inst in) {
// arrays must be aligned by 16
float *a = malloc(sizeof(float)*size);
float *b = malloc(sizeof(float)*size);
// define two arrays
for (int i = 0; i < size; i++) {
b[i] = rand();
}
omp_set_num_threads(in.num_threads);
#pragma omp parallel
while (1){
AddTwo(a, b, in.num_threads); // call AddTwo function}
if (in.avx)
avx();
if (in.sse4)
sse4();
if (in.sse3)
sse3();
if (in.ssse3)
ssse3();
if (in.aes)
aes();
if (in.pclmul)
pclmul();
if (in.rdrand)
rdrand();
if (in.fma4)
fma4();
if (in.xop)
xop();
if (in.sse4a)
sse4a();
printf("Stress round.\n");
}
free(a);
free(b);
}
int main(int argc, char **argv) {
int c;
int digit_optind = 0;
int opt_count = 0;
int ret = 0;
while (1) {
int this_option_optind = optind ? optind : 1;
int option_index = 0;
static struct option long_options[] =
{{ "stress",required_argument, 0, 0 },
{ "stressmem", required_argument, 0, 0 },
{ "sse3", no_argument, 0, 0 },
{ "ssse3", no_argument, 0, 0 },
{ "sse4", no_argument, 0, 0 },
{ "sse4a", no_argument, 0, 0 },
{ "avx", no_argument, 0, 0 },
{ "aes", no_argument, 0, 0 },
{ "pclmul", no_argument, 0, 0 },
{ "rdrand", no_argument, 0, 0 },
{ "fma4", no_argument, 0, 0 },
{ "xop", no_argument, 0, 0 },
{ 0, 0, 0, 0}};
c = getopt_long(argc, argv, "", long_options, &option_index);
if (c == -1){
if (!opt_count)
print_help();
break;
}
switch (c) {
case 0:
switch (option_index) {
case 0:
stress(parse_Inst(optarg));
break;
case 1:
stressmem(atoi(optarg));
break;
case 2:
ret += sse3();
break;
case 3:
ret += ssse3();
break;
case 4:
ret += sse4();
break;
case 5:
ret += sse4a();
break;
case 6:
ret += avx();
break;
case 7:
ret += aes();
break;
case 8:
ret += pclmul();
break;
case 9:
ret += rdrand();
break;
case 10:
ret += fma4();
break;
case 11:
ret += xop();
break;
}
break;
case '?':
print_help();
break;
default:
printf("?? getopt returned character code 0%o ??\n", c);
break;
}
opt_count += 1;
}
if (ret > 0) {
printf("%d test fail.\n", ret);
exit(-1);
}
exit(0);
}
void
time_rdrandom(void)
{
TIME_UNSIGNED_RNG(rdrand());
}
/*
* Determine i/o configuration for a machine.
*/
void
cpu_configure(void)
{
/*
* Note, on i386, configure is not running under splhigh unlike other
* architectures. This fact is used by the pcmcia irq line probing.
*/
gdt_init(); /* XXX - pcibios uses gdt stuff */
/* Set up proc0's TSS */
i386_proc0_tss_init();
#ifdef KVM86
kvm86_init();
#endif
pmap_bootstrap_pae();
#if defined(MULTIPROCESSOR) || \
(NACPI > 0 && !defined(SMALL_KERNEL))
/* install the lowmem ptp after boot args for 1:1 mappings */
pmap_prealloc_lowmem_ptp();
#endif
#ifdef MULTIPROCESSOR
pmap_kenter_pa((vaddr_t)MP_TRAMPOLINE, /* virtual */
(paddr_t)MP_TRAMPOLINE, /* physical */
PROT_READ | PROT_WRITE | PROT_EXEC); /* protection */
pmap_kenter_pa((vaddr_t)MP_TRAMP_DATA, /* virtual */
(paddr_t)MP_TRAMP_DATA, /* physical */
PROT_READ | PROT_WRITE); /* protection */
#endif
if (config_rootfound("mainbus", NULL) == NULL)
panic("cpu_configure: mainbus not configured");
#if NIOAPIC > 0
ioapic_enable();
#endif
proc0.p_addr->u_pcb.pcb_cr0 = rcr0();
#ifdef MULTIPROCESSOR
/* propagate TSS configuration to the idle pcb's. */
cpu_init_idle_pcbs();
#endif
spl0();
/*
* We can not know which is our root disk, defer
* until we can checksum blocks to figure it out.
*/
cold = 0;
/*
* At this point the RNG is running, and if FSXR is set we can
* use it. Here we setup a periodic timeout to collect the data.
*/
if (viac3_rnd_present) {
timeout_set(&viac3_rnd_tmo, viac3_rnd, &viac3_rnd_tmo);
viac3_rnd(&viac3_rnd_tmo);
}
if (has_rdrand || has_rdseed) {
timeout_set(&rdrand_tmo, rdrand, &rdrand_tmo);
rdrand(&rdrand_tmo);
}
#ifdef CRYPTO
/*
* Also, if the chip has crypto available, enable it.
*/
if (i386_has_xcrypt)
viac3_crypto_setup();
#endif
}
