static void nlm_init_node(void)
{
struct nlm_soc_info *nodep;
nodep = nlm_current_node();
nodep->picbase = nlm_mmio_base(NETLOGIC_IO_PIC_OFFSET);
nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
spin_lock_init(&nodep->piclock);
}
PUBLIC
void
Jdb_kern_info_cpu::dump_cp0_regs()
{
Mword val;
DUMP_CP0("EBase", read_c0_ebase(), val);
DUMP_INT("Ebase.CPUNum", (val & 0x3ff));
DUMP_CP0("EntryHi", read_c0_entryhi(), val);
DUMP_HEX("EntryHi.ASID", (val & 0xff));
DUMP_CP0("EPC", read_c0_epc(), val);
DUMP_CP0("Status", read_c0_status(), val);
DUMP_CP0("Cause", read_c0_cause(), val);
DUMP_CP0("PRId", read_c0_prid(), val);
DUMP_CP0("HWREna", read_c0_hwrena(), val);
DUMP_CP0("Config", read_c0_config(), val);
if (val & MIPS_CONF_M) {
DUMP_CP0("Config1", read_c0_config1(), val);
if (val & MIPS_CONF_M) {
DUMP_CP0("Config2", read_c0_config2(), val);
if (val & MIPS_CONF_M) {
DUMP_CP0("Config3", read_c0_config3(), val);
if (val & MIPS_CONF3_ULRI)
DUMP_CP0("UserLocal", read_c0_userlocal(), val);
}
}
}
if (cpu_has_vz)
DUMP_CP0("GuestCtl0", read_c0_guestctl0(), val);
if (cpu_has_guestctl0ext)
DUMP_CP0("GuestCtl0Ext", read_c0_guestctl0ext(), val);
if (cpu_has_vz)
DUMP_CP0("GTOffset", read_c0_gtoffset(), val);
if (cpu_has_guestctl1) {
DUMP_CP0("GuestCtl1", read_c0_guestctl1(), val);
DUMP_HEX("GuestCtl1.ID", (val & GUESTCTL1_ID));
}
if (cpu_has_guestctl2) {
DUMP_CP0("GuestCtl2", read_c0_guestctl2(), val);
DUMP_HEX("GuestCtl2.VIP", (val & GUESTCTL2_VIP));
}
}
void __init prom_init(void)
{
int *argv, *envp; /* passed as 32 bit ptrs */
struct psb_info *prom_infop;
/* truncate to 32 bit and sign extend all args */
argv = (int *)(long)(int)fw_arg1;
envp = (int *)(long)(int)fw_arg2;
prom_infop = (struct psb_info *)(long)(int)fw_arg3;
nlm_prom_info = *prom_infop;
nlm_early_serial_setup();
build_arcs_cmdline(argv);
nlm_common_ebase = read_c0_ebase() & (~((1 << 12) - 1));
prom_add_memory();
#ifdef CONFIG_SMP
nlm_wakeup_secondary_cpus(nlm_prom_info.online_cpu_map);
register_smp_ops(&nlm_smp_ops);
#endif
}
void octeon_hal_init(void)
{
/* Make sure we got the boot descriptor block */
if ((octeon_boot_desc_ptr == (void *)0xEADBEEFULL))
panic("Boot descriptor block wasn't passed properly\n");
octeon_bootinfo = octeon_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
spin_lock_init(&octeon_led_lock);
#ifndef CONFIG_CAVIUM_OCTEON_SIMULATOR
/* Only enable the LED controller if we're running on a CN38XX or CN58XX.
The CN30XX and CN31XX don't have an LED controller */
if ((current_cpu_data.cputype == CPU_CAVIUM_CN38XX) ||
(current_cpu_data.cputype == CPU_CAVIUM_CN58XX))
{
octeon_write_csr(OCTEON_LED_EN, 0);
octeon_write_csr(OCTEON_LED_PRT, 0);
octeon_write_csr(OCTEON_LED_DBG, 0);
octeon_write_csr(OCTEON_LED_PRT_FMT, 0);
octeon_write_csr(OCTEON_LED_UDD_CNTX(0), 32);
octeon_write_csr(OCTEON_LED_UDD_CNTX(1), 32);
octeon_write_csr(OCTEON_LED_UDD_DATX(0), 0);
octeon_write_csr(OCTEON_LED_UDD_DATX(1), 0);
octeon_write_csr(OCTEON_LED_EN, 1);
}
#endif
#if CONFIG_CAVIUM_RESERVE32
{
cvmx_bootmem_desc_t *bootmem_desc = octeon_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
octeon_reserve32_memory = octeon_phy_mem_named_block_alloc(bootmem_desc, CONFIG_CAVIUM_RESERVE32<<20, 0, 0, 2<<20, "CAVIUM_RESERVE32");
if (octeon_reserve32_memory == 0)
printk("Failed to allocate CAVIUM_RESERVE32 memory area\n");
}
#endif
#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
if (octeon_read_csr(OCTEON_L2D_FUS3) & (3ull<<34))
{
printk("Skipping L2 locking due to reduced L2 cache size\n");
}
else
{
extern asmlinkage void octeon_handle_irq(void);
uint64_t ebase = read_c0_ebase() & 0x3ffff000;
#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
octeon_l2_lock_range(ebase, 0x100); /* TLB refill */
#endif
#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
octeon_l2_lock_range(ebase + 0x180, 0x80); /* General exception */
#endif
#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
octeon_l2_lock_range(ebase + 0x200, 0x80); /* Interrupt handler */
#endif
#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
octeon_l2_lock_range((uint64_t)octeon_handle_irq, 0x280);
#endif
#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
octeon_l2_lock_range((uint64_t)memcpy, 0x480);
#endif
}
#endif
}