void arm_generic_timer_init(int irq, uint32_t freq_override)
{
uint32_t cntfrq;
if (freq_override == 0) {
cntfrq = read_cntfrq();
if (!cntfrq) {
TRACEF("Failed to initialize timer, frequency is 0\n");
return;
}
} else {
cntfrq = freq_override;
}
#if LOCAL_TRACE
LTRACEF("Test min cntfrq\n");
arm_generic_timer_init_conversion_factors(1);
test_time_conversions(1);
LTRACEF("Test max cntfrq\n");
arm_generic_timer_init_conversion_factors(~0);
test_time_conversions(~0);
LTRACEF("Set actual cntfrq\n");
#endif
arm_generic_timer_init_conversion_factors(cntfrq);
test_time_conversions(cntfrq);
LTRACEF("register irq %d on cpu %d\n", irq, arch_curr_cpu_num());
register_int_handler(irq, &platform_tick, NULL);
unmask_interrupt(irq);
timer_irq = irq;
}
void dump_timer_regs(void)
{
#if 0
unsigned int cntfrq = 0xFFFFFFFF;
unsigned int cntkctl = 0xFFFFFFFF;
#endif
unsigned int cntpct_lo = 0xFFFFFFFF;
unsigned int cntpct_hi = 0xFFFFFFFF;
#if 0
unsigned int cntvct_lo = 0xFFFFFFFF;
unsigned int cntvct_hi = 0xFFFFFFFF;
#endif
unsigned int cntp_ctl = 0xFFFFFFFF;
unsigned int cntp_cval_lo = 0xFFFFFFFF;
unsigned int cntp_cval_hi = 0xFFFFFFFF;
unsigned int cntp_tval = 0xFFFFFFFF;
#if 0
unsigned int cntv_ctl = 0xFFFFFFFF;
unsigned int cntv_cval_lo = 0xFFFFFFFF;
unsigned int cntv_cval_hi = 0xFFFFFFFF;
unsigned int cntv_tval = 0xFFFFFFFF;
#endif
#if 0
read_cntfrq(cntfrq);
read_cntkctl(cntkctl);
#endif
read_cntpct(cntpct_lo, cntpct_hi);
#if 0
read_cntvct(cntvct_lo, cntvct_hi);
#endif
read_cntp_ctl(cntp_ctl);
read_cntp_cval(cntp_cval_lo, cntp_cval_hi);
read_cntp_tval(cntp_tval);
#if 0
read_cntv_ctl(cntv_ctl);
read_cntv_cval(cntv_cval_lo, cntv_cval_hi);
read_cntv_tval(cntv_tval);
#endif
#if 0
printk("[ca7_timer]0. cntfrq = 0x%x\n", cntfrq);
printk("[ca7_timer]1. cntkctl = 0x%x\n", cntkctl);
#endif
printk("[ca7_timer]2. cntpct_lo = 0x%08x, cntpct_hi = 0x%08x\n", cntpct_lo, cntpct_hi);
#if 0
printk("[ca7_timer]3. cntvct_lo = 0x%08x, cntvct_hi = 0x%08x\n", cntvct_lo, cntvct_hi);
#endif
printk("[ca7_timer]4. cntp_ctl = 0x%x\n", cntp_ctl);
printk("[ca7_timer]5. cntp_cval_lo = 0x%08x, cntp_cval_hi = 0x%08x\n", cntp_cval_lo, cntp_cval_hi);
printk("[ca7_timer]6. cntp_tval = 0x%08x\n", cntp_tval);
#if 0
printk("[ca7_timer]7. cntv_ctl = 0x%x\n", cntv_ctl);
printk("[ca7_timer]8. cntv_cval_lo = 0x%08x, cntv_cval_hi = 0x%08x\n", cntv_cval_lo, cntv_cval_hi);
printk("[ca7_timer]9. cntv_tval = 0x%08x\n", cntv_tval);
#endif
}
static void primary_save_cntfrq(void)
{
assert(cntfrq == 0);
/*
* CNTFRQ should be initialized on the primary CPU by a
* previous boot stage
*/
cntfrq = read_cntfrq();
}
void plat_cpu_reset_late(void)
{
static uint32_t cntfrq;
vaddr_t addr;
if (!get_core_pos()) {
/* read cnt freq */
cntfrq = read_cntfrq();
#if defined(CFG_BOOT_SECONDARY_REQUEST)
/* set secondary entry address */
write32(__compiler_bswap32(CFG_TEE_LOAD_ADDR),
DCFG_BASE + DCFG_SCRATCHRW1);
/* release secondary cores */
write32(__compiler_bswap32(0x1 << 1), /* cpu1 */
DCFG_BASE + DCFG_CCSR_BRR);
dsb();
sev();
#endif
/* configure CSU */
/* first grant all peripherals */
for (addr = CSU_BASE + CSU_CSL_START;
addr != CSU_BASE + CSU_CSL_END;
addr += 4)
write32(__compiler_bswap32(CSU_ACCESS_ALL), addr);
/* restrict key preipherals from NS */
write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY),
CSU_BASE + CSU_CSL30);
write32(__compiler_bswap32(CSU_ACCESS_SEC_ONLY),
CSU_BASE + CSU_CSL37);
/* lock the settings */
for (addr = CSU_BASE + CSU_CSL_START;
addr != CSU_BASE + CSU_CSL_END;
addr += 4)
write32(read32(addr) |
__compiler_bswap32(CSU_SETTING_LOCK),
addr);
} else {
/* program the cntfrq, the cntfrq is banked for each core */
write_cntfrq(cntfrq);
}
}
static TEE_Result gprof_start_pc_sampling(struct tee_ta_session *s,
uint32_t param_types,
TEE_Param params[TEE_NUM_PARAMS])
{
uint32_t exp_pt = TEE_PARAM_TYPES(TEE_PARAM_TYPE_MEMREF_INOUT,
TEE_PARAM_TYPE_VALUE_INPUT,
TEE_PARAM_TYPE_NONE,
TEE_PARAM_TYPE_NONE);
struct sample_buf *sbuf;
uint32_t offset;
uint32_t scale;
TEE_Result res;
uint32_t len;
uaddr_t buf;
if (exp_pt != param_types)
return TEE_ERROR_BAD_PARAMETERS;
buf = (uaddr_t)params[0].memref.buffer;
len = params[0].memref.size;
offset = params[1].value.a;
scale = params[1].value.b;
res = tee_mmu_check_access_rights(to_user_ta_ctx(s->ctx),
TEE_MEMORY_ACCESS_WRITE |
TEE_MEMORY_ACCESS_ANY_OWNER,
buf, len);
if (res != TEE_SUCCESS)
return res;
sbuf = calloc(1, sizeof(*sbuf));
if (!sbuf)
return TEE_ERROR_OUT_OF_MEMORY;
sbuf->samples = (uint16_t *)buf;
sbuf->nsamples = len / sizeof(*sbuf->samples);
sbuf->offset = offset;
sbuf->scale = scale;
sbuf->freq = read_cntfrq();
sbuf->enabled = true;
s->sbuf = sbuf;
return TEE_SUCCESS;
}
static void test_start_timer(void)
{
uint32_t ctl;
uint32_t tval;
uint64_t pct;
HVMM_TRACE_ENTER();
/* every second */
tval = read_cntfrq();
write_cntp_tval(tval);
pct = read_cntpct();
uart_print("cntpct:");
uart_print_hex64(pct);
uart_print("\n\r");
uart_print("cntp_tval:");
uart_print_hex32(tval);
uart_print("\n\r");
/* enable timer */
ctl = read_cntp_ctl();
ctl |= 0x1;
write_cntp_ctl(ctl);
HVMM_TRACE_EXIT();
}
