static void build_regrestore_cmds(struct adreno_device *adreno_dev, struct adreno_context *drawctxt) { unsigned int *start = tmp_ctx.cmd; unsigned int *cmd = start; unsigned int i = 0; unsigned int reg_array_size = 0; const unsigned int *ptr_register_ranges; *cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmd++ = 0; /* H/W Registers */ /* deferred cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, ???); */ cmd++; #ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES /* Force mismatch */ *cmd++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) | 1; #else *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000; #endif /* Based on chip id choose the registers ranges*/ if (adreno_is_a220(adreno_dev)) { ptr_register_ranges = register_ranges_a220; reg_array_size = ARRAY_SIZE(register_ranges_a220); } else if (adreno_is_a225(adreno_dev)) { ptr_register_ranges = register_ranges_a225; reg_array_size = ARRAY_SIZE(register_ranges_a225); } else { ptr_register_ranges = register_ranges_a20x; reg_array_size = ARRAY_SIZE(register_ranges_a20x); } for (i = 0; i < (reg_array_size/2); i++) { cmd = reg_range(cmd, ptr_register_ranges[i*2], ptr_register_ranges[i*2+1]); } /* Now we know how many register blocks we have, we can compute command * length */ start[2] = cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, (cmd - start) - 3); /* Enable shadowing for the entire register block. */ #ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES start[4] |= (0 << 24) | (4 << 16); /* Disable shadowing. */ #else start[4] |= (1 << 24) | (4 << 16); #endif /* Need to handle some of the registers separately */ *cmd++ = cp_type0_packet(REG_SQ_GPR_MANAGEMENT, 1); tmp_ctx.reg_values[0] = virt2gpu(cmd, &drawctxt->gpustate); *cmd++ = 0x00040400; *cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmd++ = 0; *cmd++ = cp_type0_packet(REG_TP0_CHICKEN, 1); tmp_ctx.reg_values[1] = virt2gpu(cmd, &drawctxt->gpustate); *cmd++ = 0x00000000; if (adreno_is_a22x(adreno_dev)) { unsigned int i; unsigned int j = 2; for (i = REG_A220_VSC_BIN_SIZE; i <= REG_A220_VSC_PIPE_DATA_LENGTH_7; i++) { *cmd++ = cp_type0_packet(i, 1); tmp_ctx.reg_values[j] = virt2gpu(cmd, &drawctxt->gpustate); *cmd++ = 0x00000000; j++; } } /* ALU Constants */ *cmd++ = cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, 3); *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000; #ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES *cmd++ = (0 << 24) | (0 << 16) | 0; /* Disable shadowing */ #else *cmd++ = (1 << 24) | (0 << 16) | 0; #endif *cmd++ = ALU_CONSTANTS; /* Texture Constants */ *cmd++ = cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, 3); *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000; #ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES /* Disable shadowing */ *cmd++ = (0 << 24) | (1 << 16) | 0; #else *cmd++ = (1 << 24) | (1 << 16) | 0; #endif *cmd++ = TEX_CONSTANTS; /* Boolean Constants */ *cmd++ = cp_type3_packet(CP_SET_CONSTANT, 1 + BOOL_CONSTANTS); *cmd++ = (2 << 16) | 0; /* the next BOOL_CONSTANT dwords is the shadow area for * boolean constants. */ tmp_ctx.bool_shadow = virt2gpu(cmd, &drawctxt->gpustate); cmd += BOOL_CONSTANTS; /* Loop Constants */ *cmd++ = cp_type3_packet(CP_SET_CONSTANT, 1 + LOOP_CONSTANTS); *cmd++ = (3 << 16) | 0; /* the next LOOP_CONSTANTS dwords is the shadow area for * loop constants. */ tmp_ctx.loop_shadow = virt2gpu(cmd, &drawctxt->gpustate); cmd += LOOP_CONSTANTS; /* create indirect buffer command for above command sequence */ create_ib1(drawctxt, drawctxt->reg_restore, start, cmd); tmp_ctx.cmd = cmd; }
static void build_regrestore_cmds(struct adreno_device *adreno_dev, struct adreno_context *drawctxt) { unsigned int *start = tmp_ctx.cmd; unsigned int *cmd = start; unsigned int i = 0; unsigned int reg_array_size = 0; const unsigned int *ptr_register_ranges; *cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmd++ = 0; cmd++; #ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES *cmd++ = ((drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000) | 1; #else *cmd++ = (drawctxt->gpustate.gpuaddr + REG_OFFSET) & 0xFFFFE000; #endif if (adreno_is_a220(adreno_dev)) { ptr_register_ranges = register_ranges_a220; reg_array_size = ARRAY_SIZE(register_ranges_a220); } else if (adreno_is_a225(adreno_dev)) { ptr_register_ranges = register_ranges_a225; reg_array_size = ARRAY_SIZE(register_ranges_a225); } else { ptr_register_ranges = register_ranges_a20x; reg_array_size = ARRAY_SIZE(register_ranges_a20x); } for (i = 0; i < (reg_array_size/2); i++) { cmd = reg_range(cmd, ptr_register_ranges[i*2], ptr_register_ranges[i*2+1]); } start[2] = cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, (cmd - start) - 3); #ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES start[4] |= (0 << 24) | (4 << 16); #else start[4] |= (1 << 24) | (4 << 16); #endif *cmd++ = cp_type0_packet(REG_SQ_GPR_MANAGEMENT, 1); tmp_ctx.reg_values[0] = virt2gpu(cmd, &drawctxt->gpustate); *cmd++ = 0x00040400; *cmd++ = cp_type3_packet(CP_WAIT_FOR_IDLE, 1); *cmd++ = 0; *cmd++ = cp_type0_packet(REG_TP0_CHICKEN, 1); tmp_ctx.reg_values[1] = virt2gpu(cmd, &drawctxt->gpustate); *cmd++ = 0x00000000; if (adreno_is_a20x(adreno_dev)) { *cmd++ = cp_type0_packet(REG_RB_BC_CONTROL, 1); tmp_ctx.reg_values[2] = virt2gpu(cmd, &drawctxt->gpustate); *cmd++ = 0x00000000; } if (adreno_is_a22x(adreno_dev)) { unsigned int i; unsigned int j = 2; for (i = REG_A220_VSC_BIN_SIZE; i <= REG_A220_VSC_PIPE_DATA_LENGTH_7; i++) { *cmd++ = cp_type0_packet(i, 1); tmp_ctx.reg_values[j] = virt2gpu(cmd, &drawctxt->gpustate); *cmd++ = 0x00000000; j++; } } *cmd++ = cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, 3); *cmd++ = drawctxt->gpustate.gpuaddr & 0xFFFFE000; #ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES *cmd++ = (0 << 24) | (0 << 16) | 0; #else *cmd++ = (1 << 24) | (0 << 16) | 0; #endif *cmd++ = ALU_CONSTANTS; *cmd++ = cp_type3_packet(CP_LOAD_CONSTANT_CONTEXT, 3); *cmd++ = (drawctxt->gpustate.gpuaddr + TEX_OFFSET) & 0xFFFFE000; #ifdef CONFIG_MSM_KGSL_DISABLE_SHADOW_WRITES *cmd++ = (0 << 24) | (1 << 16) | 0; #else *cmd++ = (1 << 24) | (1 << 16) | 0; #endif *cmd++ = TEX_CONSTANTS; *cmd++ = cp_type3_packet(CP_SET_CONSTANT, 1 + BOOL_CONSTANTS); *cmd++ = (2 << 16) | 0; tmp_ctx.bool_shadow = virt2gpu(cmd, &drawctxt->gpustate); cmd += BOOL_CONSTANTS; *cmd++ = cp_type3_packet(CP_SET_CONSTANT, 1 + LOOP_CONSTANTS); *cmd++ = (3 << 16) | 0; tmp_ctx.loop_shadow = virt2gpu(cmd, &drawctxt->gpustate); cmd += LOOP_CONSTANTS; create_ib1(drawctxt, drawctxt->reg_restore, start, cmd); tmp_ctx.cmd = cmd; }