void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
{
MIPSnetState *s;
qemu_check_nic_model(nd, "mipsnet");
s = qemu_mallocz(sizeof(MIPSnetState));
register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
s->io_base = base;
s->irq = irq;
if (nd) {
memcpy(s->conf.macaddr.a, nd->macaddr, sizeof(nd->macaddr));
s->conf.vlan = nd->vlan;
s->conf.peer = nd->netdev;
s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
nd->model, nd->name, s);
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
}
mipsnet_reset(s);
vmstate_register(NULL, 0, &vmstate_mipsnet, s);
}
static void bmdma_map(PCIDevice *pci_dev, int region_num,
pcibus_t addr, pcibus_t size, int type)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
int i;
for(i = 0;i < 2; i++) {
BMDMAState *bm = &d->bmdma[i];
d->bus[i].bmdma = bm;
bm->bus = d->bus+i;
qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
register_ioport_read(addr, 4, 1, bmdma_readb, bm);
register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
addr += 8;
}
}
/* If fd is zero, it means that the parallel device uses the console */
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
{
ParallelState *s;
uint8_t dummy;
s = (ParallelState *)qemu_mallocz(sizeof(ParallelState));
if (!s)
return NULL;
parallel_reset(s, irq, chr);
if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
s->hw_driver = 1;
s->status = dummy;
}
if (s->hw_driver) {
register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
}
else {
register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
}
return s;
}
void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
{
MIPSnetState *s;
qemu_check_nic_model(nd, "mipsnet");
s = qemu_mallocz(sizeof(MIPSnetState));
register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
s->io_base = base;
s->irq = irq;
if (nd && nd->vlan) {
s->vc = nd->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
mipsnet_receive,
mipsnet_can_receive,
mipsnet_cleanup, s);
} else {
s->vc = NULL;
}
qemu_format_nic_info_str(s->vc, nd->macaddr);
mipsnet_reset(s);
register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
}
static int parallel_isa_initfn(ISADevice *dev)
{
static int index;
ISAParallelState *isa = DO_UPCAST(ISAParallelState, dev, dev);
ParallelState *s = &isa->state;
int base;
uint8_t dummy;
if (!s->chr) {
fprintf(stderr, "Can't create parallel device, empty char device\n");
exit(1);
}
if (isa->index == -1)
isa->index = index;
if (isa->index >= MAX_PARALLEL_PORTS)
return -1;
if (isa->iobase == -1)
isa->iobase = isa_parallel_io[isa->index];
index++;
base = isa->iobase;
isa_init_irq(dev, &s->irq, isa->isairq);
qemu_register_reset(parallel_reset, s);
if (qemu_chr_fe_ioctl(s->chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
s->hw_driver = 1;
s->status = dummy;
}
if (s->hw_driver) {
register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s);
register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s);
isa_init_ioport_range(dev, base, 8);
register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s);
register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s);
register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s);
register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s);
isa_init_ioport(dev, base+4);
register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s);
register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s);
isa_init_ioport_range(dev, base+0x400, 8);
}
else {
register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s);
register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s);
isa_init_ioport_range(dev, base, 8);
}
return 0;
}
void ioport_register(IORange *ioport)
{
register_ioport_read(ioport->base, ioport->len, 1,
ioport_readb_thunk, ioport);
register_ioport_read(ioport->base, ioport->len, 2,
ioport_readw_thunk, ioport);
register_ioport_read(ioport->base, ioport->len, 4,
ioport_readl_thunk, ioport);
register_ioport_write(ioport->base, ioport->len, 1,
ioport_writeb_thunk, ioport);
register_ioport_write(ioport->base, ioport->len, 2,
ioport_writew_thunk, ioport);
register_ioport_write(ioport->base, ioport->len, 4,
ioport_writel_thunk, ioport);
}
void kbd_init(void)
{
KBDState *s = &kbd_state;
kbd_reset(s);
register_savevm("pckbd", 0, 3, kbd_save, kbd_load, s);
register_ioport_read(0x60, 1, 1, kbd_read_data, s);
register_ioport_write(0x60, 1, 1, kbd_write_data, s);
register_ioport_read(0x64, 1, 1, kbd_read_status, s);
register_ioport_write(0x64, 1, 1, kbd_write_command, s);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
qemu_register_reset(kbd_reset, s);
}
void ioport_register(IORange *ioport)
{
register_ioport_read(ioport->base, ioport->len, 1,
ioport_readb_thunk, ioport);
register_ioport_read(ioport->base, ioport->len, 2,
ioport_readw_thunk, ioport);
register_ioport_read(ioport->base, ioport->len, 4,
ioport_readl_thunk, ioport);
register_ioport_write(ioport->base, ioport->len, 1,
ioport_writeb_thunk, ioport);
register_ioport_write(ioport->base, ioport->len, 2,
ioport_writew_thunk, ioport);
register_ioport_write(ioport->base, ioport->len, 4,
ioport_writel_thunk, ioport);
ioport_destructor_table[ioport->base] = iorange_destructor_thunk;
}
RTCState *rtc_init(int base, int irq)
{
RTCState *s;
time_t ti;
struct tm *tm;
int val;
s = qemu_mallocz(sizeof(RTCState));
if (!s)
return NULL;
/* PC cmos mappings */
#define REG_IBM_CENTURY_BYTE 0x32
#define REG_IBM_PS2_CENTURY_BYTE 0x37
time(&ti);
tm = gmtime(&ti); /* XXX localtime and update from guest? */
val = to_bcd(s, (tm->tm_year / 100) + 19);
rtc_set_memory(s, REG_IBM_CENTURY_BYTE, val);
rtc_set_memory(s, REG_IBM_PS2_CENTURY_BYTE, val);
register_ioport_write(base, 2, 1, cmos_ioport_write, s);
register_ioport_read(base, 2, 1, cmos_ioport_read, s);
register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
return s;
}
static int rtc_initfn(ISADevice *dev)
{
RTCState *s = DO_UPCAST(RTCState, dev, dev);
int base = 0x70;
s->cmos_data[RTC_REG_A] = 0x26;
s->cmos_data[RTC_REG_B] = 0x02;
s->cmos_data[RTC_REG_C] = 0x00;
s->cmos_data[RTC_REG_D] = 0x80;
rtc_set_date_from_host(dev);
s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s);
#ifdef TARGET_I386
if (rtc_td_hack)
s->coalesced_timer =
qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s);
#endif
s->second_timer = qemu_new_timer_ns(rtc_clock, rtc_update_second, s);
s->second_timer2 = qemu_new_timer_ns(rtc_clock, rtc_update_second2, s);
s->next_second_time =
qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100;
qemu_mod_timer(s->second_timer2, s->next_second_time);
register_ioport_write(base, 2, 1, cmos_ioport_write, s);
register_ioport_read(base, 2, 1, cmos_ioport_read, s);
isa_init_ioport_range(dev, base, 2);
qdev_set_legacy_instance_id(&dev->qdev, base, 2);
qemu_register_reset(rtc_reset, s);
return 0;
}
RTCState *rtc_init(int base, qemu_irq irq, int base_year)
{
RTCState *s;
s = qemu_mallocz(sizeof(RTCState));
s->irq = irq;
s->cmos_data[RTC_REG_A] = 0x26;
s->cmos_data[RTC_REG_B] = 0x02;
s->cmos_data[RTC_REG_C] = 0x00;
s->cmos_data[RTC_REG_D] = 0x80;
s->base_year = base_year;
rtc_set_date_from_host(s);
s->periodic_timer = qemu_new_timer(vm_clock,
rtc_periodic_timer, s);
s->second_timer = qemu_new_timer(vm_clock,
rtc_update_second, s);
s->second_timer2 = qemu_new_timer(vm_clock,
rtc_update_second2, s);
s->next_second_time = qemu_get_clock(vm_clock) + (ticks_per_sec * 99) / 100;
qemu_mod_timer(s->second_timer2, s->next_second_time);
register_ioport_write(base, 2, 1, cmos_ioport_write, s);
register_ioport_read(base, 2, 1, cmos_ioport_read, s);
register_savevm("mc146818rtc", base, 1, rtc_save, rtc_load, s);
#ifdef TARGET_I386
if (rtc_td_hack)
register_savevm("mc146818rtc-td", base, 1, rtc_save_td, rtc_load_td, s);
#endif
return s;
}
static void assigned_dev_ioport_map(PCIDevice *pci_dev, int region_num,
uint32_t addr, uint32_t size, int type)
{
AssignedDevice *r_dev = container_of(pci_dev, AssignedDevice, dev);
AssignedDevRegion *region = &r_dev->v_addrs[region_num];
int first_map = (region->e_size == 0);
CPUState *env;
region->e_physbase = addr;
region->e_size = size;
DEBUG("e_phys=0x%x r_baseport=%x type=0x%x len=%d region_num=%d \n",
addr, region->u.r_baseport, type, size, region_num);
if (first_map) {
struct ioperm_data *data;
data = qemu_mallocz(sizeof(struct ioperm_data));
if (data == NULL) {
fprintf(stderr, "%s: Out of memory\n", __func__);
exit(1);
}
data->start_port = region->u.r_baseport;
data->num = region->r_size;
data->turn_on = 1;
kvm_add_ioperm_data(data);
for (env = first_cpu; env; env = env->next_cpu)
kvm_ioperm(env, data);
}
register_ioport_read(addr, size, 1, assigned_dev_ioport_readb,
(r_dev->v_addrs + region_num));
register_ioport_read(addr, size, 2, assigned_dev_ioport_readw,
(r_dev->v_addrs + region_num));
register_ioport_read(addr, size, 4, assigned_dev_ioport_readl,
(r_dev->v_addrs + region_num));
register_ioport_write(addr, size, 1, assigned_dev_ioport_writeb,
(r_dev->v_addrs + region_num));
register_ioport_write(addr, size, 2, assigned_dev_ioport_writew,
(r_dev->v_addrs + region_num));
register_ioport_write(addr, size, 4, assigned_dev_ioport_writel,
(r_dev->v_addrs + region_num));
}
void apm_init(APMState *apm, apm_ctrl_changed_t callback, void *arg)
{
apm->callback = callback;
apm->arg = arg;
/* ioport 0xb2, 0xb3 */
register_ioport_write(APM_CNT_IOPORT, 2, 1, apm_ioport_writeb, apm);
register_ioport_read(APM_CNT_IOPORT, 2, 1, apm_ioport_readb, apm);
}
void vmport_init(void)
{
register_ioport_read(0x5658, 1, 4, vmport_ioport_read, &port_state);
register_ioport_write(0x5658, 1, 4, vmport_ioport_write, &port_state);
/* Register some generic port commands */
vmport_register(VMPORT_CMD_GETVERSION, vmport_cmd_get_version, NULL);
vmport_register(VMPORT_CMD_GETRAMSIZE, vmport_cmd_ram_size, NULL);
}
static void pcnet_ioport_map(PCIDevice *pci_dev, int region_num,
pcibus_t addr, pcibus_t size, int type)
{
PCNetState *d = &DO_UPCAST(PCIPCNetState, pci_dev, pci_dev)->state;
#ifdef PCNET_DEBUG_IO
printf("pcnet_ioport_map addr=0x%04"FMT_PCIBUS" size=0x%04"FMT_PCIBUS"\n",
addr, size);
#endif
register_ioport_write(addr, 16, 1, pcnet_aprom_writeb, d);
register_ioport_read(addr, 16, 1, pcnet_aprom_readb, d);
register_ioport_write(addr + 0x10, 0x10, 2, pcnet_ioport_writew, d);
register_ioport_read(addr + 0x10, 0x10, 2, pcnet_ioport_readw, d);
register_ioport_write(addr + 0x10, 0x10, 4, pcnet_ioport_writel, d);
register_ioport_read(addr + 0x10, 0x10, 4, pcnet_ioport_readl, d);
}
static int debugcon_isa_initfn(ISADevice *dev)
{
ISADebugconState *isa = DO_UPCAST(ISADebugconState, dev, dev);
DebugconState *s = &isa->state;
debugcon_init_core(s);
register_ioport_write(isa->iobase, 1, 1, debugcon_ioport_write, s);
register_ioport_read(isa->iobase, 1, 1, debugcon_ioport_read, s);
return 0;
}
static int pc98_serial_initfn(ISADevice *dev)
{
SerialPortState *s = DO_UPCAST(SerialPortState, dev, dev);
isa_init_irq(dev, &s->pic, s->irq);
register_ioport_write(0x30, 1, 1, sio_data_write, s);
register_ioport_read(0x30, 1, 1, sio_data_read, s);
isa_init_ioport(dev, 0x30);
register_ioport_write(0x32, 1, 1, sio_cmd_write, s);
register_ioport_read(0x32, 1, 1, sio_status_read, s);
isa_init_ioport(dev, 0x32);
s->sio_timer = qemu_new_timer(rt_clock, sio_timer_handler, s);
pc98_serial_reset(s);
qemu_register_reset(pc98_serial_reset, s);
return 0;
}
static int pc98_kbd_initfn(ISADevice *dev)
{
KeyBoardState *s = DO_UPCAST(KeyBoardState, dev, dev);
isa_init_irq(dev, &s->pic, s->irq);
register_ioport_write(0x41, 1, 1, sio_data_write, s);
register_ioport_read(0x41, 1, 1, sio_data_read, s);
isa_init_ioport(dev, 0x41);
register_ioport_write(0x43, 1, 1, sio_cmd_write, s);
register_ioport_read(0x43, 1, 1, sio_status_read, s);
isa_init_ioport(dev, 0x43);
s->sio_timer = qemu_new_timer(rt_clock, sio_timer_handler, s);
qemu_add_kbd_event_handler(kbd_event_handler, s);
pc98_kbd_reset(s);
qemu_register_reset(pc98_kbd_reset, s);
return 0;
}
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base)
{
KBDState *s = &kbd_state;
s->irq_kbd = kbd_irq;
s->irq_mouse = mouse_irq;
kbd_reset(s);
register_savevm("pckbd", 0, 3, kbd_save, kbd_load, s);
register_ioport_read(io_base, 1, 1, kbd_read_data, s);
register_ioport_write(io_base, 1, 1, kbd_write_data, s);
register_ioport_read(io_base + 4, 1, 1, kbd_read_status, s);
register_ioport_write(io_base + 4, 1, 1, kbd_write_command, s);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
#ifdef TARGET_I386
vmmouse_init(s->mouse);
#endif
qemu_register_reset(kbd_reset, s);
}
PCIBus *pci_prep_init(qemu_irq *pic)
{
PREPPCIState *s;
PCIDevice *d;
int PPC_io_memory;
s = qemu_mallocz(sizeof(PREPPCIState));
s->bus = pci_register_bus(prep_set_irq, prep_map_irq, pic, 0, 4);
register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s);
register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s);
register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
PPC_PCIIO_write, s);
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
/* PCI host bridge */
d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
sizeof(PCIDevice), 0, NULL, NULL);
d->config[0x00] = 0x57; // vendor_id : Motorola
d->config[0x01] = 0x10;
d->config[0x02] = 0x01; // device_id : Raven
d->config[0x03] = 0x48;
d->config[0x08] = 0x00; // revision
d->config[0x0A] = 0x00; // class_sub = pci host
d->config[0x0B] = 0x06; // class_base = PCI_bridge
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
d->config[0x0E] = 0x00; // header_type
d->config[0x34] = 0x00; // capabilities_pointer
return s->bus;
}
static int i8042_initfn(ISADevice *dev)
{
KBDState *s = &(DO_UPCAST(ISAKBDState, dev, dev)->kbd);
isa_init_irq(dev, &s->irq_kbd, 1);
isa_init_irq(dev, &s->irq_mouse, 12);
kbd_reset(s);
vmstate_register(0, &vmstate_kbd, s);
register_ioport_read(0x60, 1, 1, kbd_read_data, s);
register_ioport_write(0x60, 1, 1, kbd_write_data, s);
register_ioport_read(0x64, 1, 1, kbd_read_status, s);
register_ioport_write(0x64, 1, 1, kbd_write_command, s);
s->kbd = ps2_kbd_init(kbd_update_kbd_irq, s);
s->mouse = ps2_mouse_init(kbd_update_aux_irq, s);
#ifdef TARGET_I386
vmmouse_init(s->mouse);
#endif
qemu_register_reset(kbd_reset, s);
return 0;
}
static void ide_map(PCIDevice *pci_dev, int region_num,
pcibus_t addr, pcibus_t size, int type)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
IDEBus *bus;
if (region_num <= 3) {
bus = &d->bus[(region_num >> 1)];
if (region_num & 1) {
register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
} else {
register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
/* data ports */
register_ioport_write(addr, 2, 2, ide_data_writew, bus);
register_ioport_read(addr, 2, 2, ide_data_readw, bus);
register_ioport_write(addr, 4, 4, ide_data_writel, bus);
register_ioport_read(addr, 4, 4, ide_data_readl, bus);
}
}
PCIBus *pci_prep_init(qemu_irq *pic)
{
PREPPCIState *s;
PCIDevice *d;
int PPC_io_memory;
s = qemu_mallocz(sizeof(PREPPCIState));
s->bus = pci_register_bus(prep_set_irq, prep_map_irq, pic, 0, 4);
register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s);
register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s);
register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
PPC_PCIIO_write, s);
cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
/* PCI host bridge */
d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
sizeof(PCIDevice), 0, NULL, NULL);
pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
d->config[0x08] = 0x00; // revision
pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
d->config[0x0C] = 0x08; // cache_line_size
d->config[0x0D] = 0x10; // latency_timer
d->config[0x0E] = 0x00; // header_type
d->config[0x34] = 0x00; // capabilities_pointer
return s->bus;
}
void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
{
MIPSnetState *s;
s = qemu_mallocz(sizeof(MIPSnetState));
if (!s)
return;
register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
s->irq = irq;
s->nd = nd;
if (nd && nd->vlan) {
s->vc = qemu_new_vlan_client(nd->vlan, mipsnet_receive,
mipsnet_can_receive, s);
} else {
s->vc = NULL;
}
snprintf(s->vc->info_str, sizeof(s->vc->info_str),
"mipsnet macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
s->nd->macaddr[0],
s->nd->macaddr[1],
s->nd->macaddr[2],
s->nd->macaddr[3],
s->nd->macaddr[4],
s->nd->macaddr[5]);
mipsnet_reset(s);
register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
}
static int pc98_ide_initfn(ISADevice *dev)
{
PC98IDEState *s = DO_UPCAST(PC98IDEState, dev, dev);
int i;
ide_bus_new(&s->bus[0], &s->dev.qdev, 0);
ide_bus_new(&s->bus[1], &s->dev.qdev, 1);
isa_init_irq(dev, &s->irq, s->isairq);
ide_init2(&s->bus[0], s->irq);
ide_init2(&s->bus[1], s->irq);
register_ioport_write(0xf0, 1, 1, pc98_ide_cpu_shutdown, s);
register_ioport_read(0xf0, 1, 1, pc98_ide_connection_read, s);
isa_init_ioport(dev, 0xf0);
register_ioport_write(0x430, 1, 1, pc98_ide_bank_write, s);
register_ioport_read(0x430, 1, 1, pc98_ide_bank_read, s);
isa_init_ioport(dev, 0x430);
register_ioport_write(0x432, 1, 1, pc98_ide_bank_write, s);
register_ioport_read(0x432, 1, 1, pc98_ide_bank_read, s);
isa_init_ioport(dev, 0x432);
for (i = 0; i < 8; i++) {
register_ioport_write(0x640 + (i << 1), 1, 1, pc98_ide_ioport_write, s);
register_ioport_read(0x640 + (i << 1), 1, 1, pc98_ide_ioport_read, s);
isa_init_ioport(dev, 0x640 + (i << 1));
}
register_ioport_write(0x640, 2, 2, pc98_ide_data_writew, s);
register_ioport_read(0x640, 2, 2, pc98_ide_data_readw, s);
/*isa_init_ioport_range(dev, 0x640, 2);*/
register_ioport_write(0x640, 4, 4, pc98_ide_data_writel, s);
register_ioport_read(0x640, 4, 4, pc98_ide_data_readl, s);
/*isa_init_ioport_range(dev, 0x640, 4);*/
register_ioport_write(0x74c, 1, 1, pc98_ide_digital_write, s);
register_ioport_read(0x74c, 1, 1, pc98_ide_status_read, s);
isa_init_ioport(dev, 0x74c);
register_ioport_read(0x74e, 1, 1, pc98_ide_digital_read, s);
isa_init_ioport(dev, 0x74e);
vmstate_register(&dev->qdev, 0, &vmstate_ide_pc98, s);
pc98_ide_reset(&dev->qdev);
return 0;
};
void *vmmouse_init(void *m)
{
VMMouseState *s = NULL;
DPRINTF("vmmouse_init\n");
s = qemu_mallocz(sizeof(VMMouseState));
if (!s)
return NULL;
s->status = 0xffff;
s->ps2_mouse = m;
register_ioport_read(0x5658, 1, 4, vmmouse_ioport_read, s);
register_savevm("vmmouse", 0, 0, vmmouse_save, vmmouse_load, s);
return s;
}
static void bmdma_map(PCIDevice *pci_dev, int region_num,
pcibus_t addr, pcibus_t size, int type)
{
PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, pci_dev);
int i;
for(i = 0;i < 2; i++) {
BMDMAState *bm = &d->bmdma[i];
register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
register_ioport_read(addr, 4, 1, bmdma_readb, bm);
iorange_init(&bm->addr_ioport, &bmdma_addr_ioport_ops, addr + 4, 4);
ioport_register(&bm->addr_ioport);
addr += 8;
}
}
FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
{
FWCfgState *s;
int io_ctl_memory, io_data_memory;
s = qemu_mallocz(sizeof(FWCfgState));
if (ctl_port) {
register_ioport_write(ctl_port, 2, 2, fw_cfg_io_writew, s);
}
if (data_port) {
register_ioport_read(data_port, 1, 1, fw_cfg_io_readb, s);
register_ioport_write(data_port, 1, 1, fw_cfg_io_writeb, s);
}
if (ctl_addr) {
io_ctl_memory = cpu_register_io_memory(fw_cfg_ctl_mem_read,
fw_cfg_ctl_mem_write, s);
cpu_register_physical_memory(ctl_addr, FW_CFG_SIZE, io_ctl_memory);
}
if (data_addr) {
io_data_memory = cpu_register_io_memory(fw_cfg_data_mem_read,
fw_cfg_data_mem_write, s);
cpu_register_physical_memory(data_addr, FW_CFG_SIZE, io_data_memory);
}
fw_cfg_add_bytes(s, FW_CFG_SIGNATURE, (uint8_t *)"QEMU", 4);
fw_cfg_add_bytes(s, FW_CFG_UUID, qemu_uuid, 16);
fw_cfg_add_i16(s, FW_CFG_NOGRAPHIC, (uint16_t)(display_type == DT_NOGRAPHIC));
fw_cfg_add_i16(s, FW_CFG_NB_CPUS, (uint16_t)smp_cpus);
fw_cfg_add_i16(s, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
fw_cfg_add_i16(s, FW_CFG_BOOT_MENU, (uint16_t)boot_menu);
vmstate_register(-1, &vmstate_fw_cfg, s);
qemu_register_reset(fw_cfg_reset, s);
return s;
}
static int fw_cfg_init1(SysBusDevice *dev)
{
FWCfgState *s = FROM_SYSBUS(FWCfgState, dev);
int io_ctl_memory, io_data_memory;
io_ctl_memory = cpu_register_io_memory(fw_cfg_ctl_mem_read,
fw_cfg_ctl_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, FW_CFG_SIZE, io_ctl_memory);
io_data_memory = cpu_register_io_memory(fw_cfg_data_mem_read,
fw_cfg_data_mem_write, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, FW_CFG_SIZE, io_data_memory);
if (s->ctl_iobase) {
register_ioport_write(s->ctl_iobase, 2, 2, fw_cfg_io_writew, s);
}
if (s->data_iobase) {
register_ioport_read(s->data_iobase, 1, 1, fw_cfg_io_readb, s);
register_ioport_write(s->data_iobase, 1, 1, fw_cfg_io_writeb, s);
}
return 0;
}
