static int gpu_runtime_suspend(struct device *dev)
{
#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 5, 7)
release_bus_freq(BUS_FREQ_HIGH);
#endif
return 0;
}
static void mu_work_handler(struct work_struct *work)
{
int ret;
u32 irq, enable, idx, mask;
pr_debug("receive M4 message 0x%x\n", m4_message);
switch (m4_message) {
case MU_LPM_M4_REQUEST_HIGH_BUS:
request_bus_freq(BUS_FREQ_HIGH);
imx6sx_set_m4_highfreq(true);
imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX,
MU_LPM_BUS_HIGH_READY_FOR_M4);
m4_freq_low = false;
break;
case MU_LPM_M4_RELEASE_HIGH_BUS:
release_bus_freq(BUS_FREQ_HIGH);
imx6sx_set_m4_highfreq(false);
imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX,
MU_LPM_M4_FREQ_CHANGE_READY);
m4_freq_low = true;
break;
default:
if ((m4_message & MU_LPM_M4_WAKEUP_SRC_MASK) ==
MU_LPM_M4_WAKEUP_SRC_VAL) {
irq = (m4_message & MU_LPM_M4_WAKEUP_IRQ_MASK) >>
MU_LPM_M4_WAKEUP_IRQ_SHIFT;
enable = (m4_message & MU_LPM_M4_WAKEUP_ENABLE_MASK) >>
MU_LPM_M4_WAKEUP_ENABLE_SHIFT;
idx = irq / 32 - 1;
mask = 1 << irq % 32;
if (enable && can_request_irq(irq, 0)) {
ret = request_irq(irq, mcc_m4_dummy_isr,
IRQF_NO_SUSPEND, "imx-m4-dummy", NULL);
if (ret) {
pr_err("%s: register interrupt %d failed, rc %d\n",
__func__, irq, ret);
break;
}
disable_irq(irq);
m4_wake_irqs[idx] = m4_wake_irqs[idx] | mask;
}
imx_gpc_add_m4_wake_up_irq(irq, enable);
}
break;
}
static int gpu_runtime_suspend(struct device *dev)
{
release_bus_freq(BUS_FREQ_HIGH);
return 0;
}
static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
{
struct dev_pm_opp *opp;
unsigned long freq_hz, volt, volt_old;
unsigned int old_freq, new_freq;
int ret;
mutex_lock(&set_cpufreq_lock);
new_freq = freq_table[index].frequency;
freq_hz = new_freq * 1000;
old_freq = clk_get_rate(arm_clk) / 1000;
rcu_read_lock();
opp = dev_pm_opp_find_freq_ceil(cpu_dev, &freq_hz);
if (IS_ERR(opp)) {
rcu_read_unlock();
dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
mutex_unlock(&set_cpufreq_lock);
return PTR_ERR(opp);
}
volt = dev_pm_opp_get_voltage(opp);
rcu_read_unlock();
volt_old = regulator_get_voltage(arm_reg);
dev_dbg(cpu_dev, "%u MHz, %ld mV --> %u MHz, %ld mV\n",
old_freq / 1000, volt_old / 1000,
new_freq / 1000, volt / 1000);
/*
* CPU freq is increasing, so need to ensure
* that bus frequency is increased too.
*/
if (old_freq <= FREQ_396_MHZ && new_freq > FREQ_396_MHZ)
request_bus_freq(BUS_FREQ_HIGH);
/* scaling up? scale voltage before frequency */
if (new_freq > old_freq) {
if (!IS_ERR(pu_reg) && regulator_is_enabled(pu_reg)) {
ret = regulator_set_voltage_tol(pu_reg,
imx6_soc_volt[index], 0);
if (ret) {
dev_err(cpu_dev,
"failed to scale vddpu up: %d\n", ret);
mutex_unlock(&set_cpufreq_lock);
return ret;
}
}
ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
if (ret) {
dev_err(cpu_dev, "failed to scale vddsoc up: %d\n", ret);
mutex_unlock(&set_cpufreq_lock);
return ret;
}
ret = regulator_set_voltage_tol(arm_reg, volt, 0);
if (ret) {
dev_err(cpu_dev,
"failed to scale vddarm up: %d\n", ret);
mutex_unlock(&set_cpufreq_lock);
return ret;
}
}
/*
* The setpoints are selected per PLL/PDF frequencies, so we need to
* reprogram PLL for frequency scaling. The procedure of reprogramming
* PLL1 is as below.
*
* - Enable pll2_pfd2_396m_clk and reparent pll1_sw_clk to it
* - Reprogram pll1_sys_clk and reparent pll1_sw_clk back to it
* - Disable pll2_pfd2_396m_clk
*/
clk_set_parent(step_clk, pll2_pfd2_396m_clk);
clk_set_parent(pll1_sw_clk, step_clk);
if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
clk_set_rate(pll1, new_freq * 1000);
/*
* Ensure pll1_bypass is set back to pll1.
*/
clk_set_parent(pll1_bypass, pll1);
clk_set_parent(pll1_sw_clk, pll1_sys_clk);
} else
/*
* Need to ensure that PLL1 is bypassed and enabled
* before ARM-PODF is set.
*/
clk_set_parent(pll1_bypass, pll1_bypass_src);
/* Ensure the arm clock divider is what we expect */
ret = clk_set_rate(arm_clk, new_freq * 1000);
if (ret) {
dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
regulator_set_voltage_tol(arm_reg, volt_old, 0);
mutex_unlock(&set_cpufreq_lock);
return ret;
}
/* scaling down? scale voltage after frequency */
if (new_freq < old_freq) {
ret = regulator_set_voltage_tol(arm_reg, volt, 0);
if (ret) {
dev_warn(cpu_dev,
"failed to scale vddarm down: %d\n", ret);
ret = 0;
}
ret = regulator_set_voltage_tol(soc_reg, imx6_soc_volt[index], 0);
if (ret) {
dev_warn(cpu_dev, "failed to scale vddsoc down: %d\n", ret);
ret = 0;
}
if (!IS_ERR(pu_reg) && regulator_is_enabled(pu_reg)) {
ret = regulator_set_voltage_tol(pu_reg,
imx6_soc_volt[index], 0);
if (ret) {
dev_warn(cpu_dev,
"failed to scale vddpu down: %d\n",
ret);
ret = 0;
}
}
}
/*
* If CPU is dropped to the lowest level, release the need
* for a high bus frequency.
*/
if (old_freq > FREQ_396_MHZ && new_freq <= FREQ_396_MHZ)
release_bus_freq(BUS_FREQ_HIGH);
mutex_unlock(&set_cpufreq_lock);
return 0;
}
