static void usb_xhci_init(struct device *dev) { struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); u32 reg32; u16 reg16; config_t *config = dev->chip_info; /* D20:F0:74h[1:0] = 00b (set D0 state) */ reg16 = pci_read_config16(dev, XHCI_PWR_CTL_STS); reg16 &= ~PWR_CTL_SET_MASK; reg16 |= PWR_CTL_SET_D0; pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); /* Disable Compliance Mode Entry */ reg32 = read32(res2mmio(res, 0x80ec, 0)); reg32 |= (1 << 0); write32(res2mmio(res, 0x80ec, 0), reg32); /* Enable clock gating first */ usb_xhci_clock_gating(dev); if (acpi_is_wakeup_s3()) { /* Reset ports that are disabled or * polling before returning to the OS. */ usb_xhci_reset_usb3(dev, 0); } else if (config->xhci_default) { /* Route all ports to XHCI */ outb(0xca, 0xb2); } }
/* Select I2C voltage of 1.8V or 3.3V. */ static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage) { u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0)); reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK; reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage); write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32); }
static unsigned long gtt_read(unsigned long reg) { u32 val; val = read32(res2mmio(gtt_res, reg, 0)); return val; }
static void usb_ehci_init(struct device *dev) { struct resource *res; u8 *base; u32 reg32; u8 reg8; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER; reg32 |= PCI_COMMAND_SERR; pci_write_config32(dev, PCI_COMMAND, reg32); reg32 = pci_read_config32(dev, 0xdc); reg32 |= (1 << 31) | (1 << 27); pci_write_config32(dev, 0xdc, reg32); reg32 = pci_read_config32(dev, 0xfc); reg32 &= ~(3 << 2); reg32 |= (2 << 2) | (1 << 29) | (1 << 17); pci_write_config32(dev, 0xfc, reg32); /* Clear any pending port changes */ res = find_resource(dev, 0x10); base = res2mmio(res, 0, 0); reg32 = read32(base + 0x24) | (1 << 2); write32(base + 0x24, reg32); /* workaround */ reg8 = pci_read_config8(dev, 0x84); reg8 |= (1 << 4); pci_write_config8(dev, 0x84, reg8); printk(BIOS_DEBUG, "done.\n"); }
static void aza_init(struct device *dev) { u8 *base; struct resource *res; u32 codec_mask; printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n"); //-------------- enable AZA (SiS7502) ------------------------- { u8 temp8; int i=0; while(SiS_SiS7502_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS7502_init[i][0]); temp8 &= SiS_SiS7502_init[i][1]; temp8 |= SiS_SiS7502_init[i][2]; pci_write_config8(dev, SiS_SiS7502_init[i][0], temp8); i++; }; } //----------------------------------------------------------- // put audio to D0 state pci_write_config8(dev, 0x54,0x00); #if DEBUG_AZA { int i; printk(BIOS_DEBUG, "****** Azalia PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); for(i=0;i<0xff;i+=4){ if((i%16)==0){ printk(BIOS_DEBUG, "\n%02x: ", i); } printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } printk(BIOS_DEBUG, "\n"); } #endif res = find_resource(dev, 0x10); if(!res) return; base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "base = 0x%p\n", base); codec_mask = codec_detect(base); if(codec_mask) { printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); codecs_init(base, codec_mask); } printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n"); }
static void azalia_init(struct device *dev) { u8 *base; struct resource *res; u32 codec_mask; u32 reg32; /* Find base address */ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); /* Set Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); azalia_pch_init(dev, base); codec_mask = hda_codec_detect(base); if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); codecs_init(base, codec_mask); } }
static void hda_init(device_t dev) { struct resource *res; int codec_mask; int i; u8 *base; reg_script_run_on_dev(dev, init_ops); res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res == NULL) return; base = res2mmio(res, 0, 0); codec_mask = hda_codec_detect(base); printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask); if (!codec_mask) return; for (i = 3; i >= 0; i--) { if (!((1 << i) & codec_mask)) continue; hda_codec_init(base, i, sizeof(hdmi_codec_verb_table), hdmi_codec_verb_table); } }
/* Enable LTR Auto Mode for D23:F0. */ static void serialio_d23_ltr(struct resource *bar0) { u32 reg; /* Program BAR0 + 1008h[2] = 1b */ reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0)); reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK; write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg); /* Program BAR0 + 1010h = 0x00000000 */ write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0); /* Program BAR0 + 3Ch[30] = 1b */ reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0)); reg |= SIO_REG_SDIO_PPR_CMD12_B30; write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg); }
static void azalia_init(struct device *dev) { #if IS_ENABLED(CONFIG_MCP55_USE_AZA) u8 *base; u32 codec_mask, reg32; struct resource *res; u8 reg8; /* Set bus master. */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); pci_write_config8(dev, 0x3c, 0x0a); // TODO: Unused? reg8 = pci_read_config8(dev, 0x40); reg8 |= (1 << 3); /* Clear Clock Detect bit. */ pci_write_config8(dev, 0x40, reg8); reg8 &= ~(1 << 3); /* Keep CLKDETCLR from clearing the bit over and over. */ pci_write_config8(dev, 0x40, reg8); reg8 |= (1 << 2); /* Enable clock detection. */ pci_write_config8(dev, 0x40, reg8); mdelay(1); reg8 = pci_read_config8(dev, 0x40); printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1)) ? "Azalia" : "AC97"); reg8 = pci_read_config8(dev, 0x40); /* Audio control */ reg8 |= 1; /* Select Azalia mode. TODO: Control via devicetree.cb. */ pci_write_config8(dev, 0x40, reg8); reg8 = pci_read_config8(dev, 0x4d); /* Docking status. */ reg8 &= ~(1 << 7); /* Docking not supported. */ pci_write_config8(dev, 0x4d, reg8); res = find_resource(dev, 0x10); if (!res) return; /* * NOTE: This will break as soon as the Azalia gets a BAR above * 4G. Is there anything we can do about it? */ base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); codecs_init(dev, base, codec_mask); } #endif }
static void hda_init(struct device *dev) { u8 byte; u32 dword; void *base; struct resource *res; u32 codec_mask; device_t sm_dev; /* Enable azalia - PM_io 0x59[3], no ac97 in sb700. */ byte = pm_ioread(0x59); byte |= 1 << 3; pm_iowrite(0x59, byte); /* Find the SMBus */ /* FIXME: Need to find out why the call below crashes. */ /*sm_dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB700_SM, 0);*/ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); /* Set routing pin - SMBus ExtFunc (0xf8/0xfc) */ pci_write_config32(sm_dev, 0xf8, 0x00); pci_write_config8(sm_dev, 0xfc, 0xAA); /* Set INTA - SMBus 0x63 [2..0] */ byte = pci_read_config8(sm_dev, 0x63); byte &= ~0x7; byte |= 0x0; /* INTA:0x0 - INTH:0x7 */ pci_write_config8(sm_dev, 0x63, byte); /* Program the 2C to 0x437b1002 */ dword = 0x437b1002; pci_write_config32(dev, 0x2c, dword); /* Read in BAR */ /* Is this right? HDA allows for a 64-bit BAR * but this is only setup for a 32-bit one */ res = find_resource(dev, 0x10); if (!res) return; base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "base = 0x%p\n", base); codec_mask = codec_detect(base); if (codec_mask) { printk(BIOS_DEBUG, "codec_mask = %02x\n", codec_mask); codecs_init(base, codec_mask); } }
static void gma_func0_init(struct device *dev) { u32 reg32; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* PCI Init, will run VBIOS */ pci_dev_init(dev); } else { u32 physbase; struct resource *pio_res; struct northbridge_intel_pineview_config *conf = dev->chip_info; /* Find base addresses */ mmio_res = find_resource(dev, 0x10); gtt_res = find_resource(dev, 0x1c); pio_res = find_resource(dev, 0x14); physbase = pci_read_config32(dev, 0x5c) & ~0xf; if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) { printk(BIOS_SPEW, "Initializing VGA. MMIO 0x%llx\n", mmio_res->base); intel_gma_init(conf, dev, res2mmio(mmio_res, 0, 0), res2mmio(gtt_res, 0, 0), physbase, pio_res->base); } /* Linux relies on VBT for panel info. */ generate_fake_intel_oprom(&conf->gfx, dev, "$VBT PINEVIEW "); } }
static void lpc_common_init(device_t dev) { u32 dword; struct resource *res; /* I/O APIC initialization. */ res = find_resource(dev, PCI_BASE_ADDRESS_1); /* IOAPIC */ ASSERT(res != NULL); setup_ioapic(res2mmio(res, 0, 0), 0); /* Don't rename IOAPIC ID. */ #if 1 dword = pci_read_config32(dev, 0xe4); dword |= (1 << 23); pci_write_config32(dev, 0xe4, dword); #endif }
static void oxford_oxpcie_enable(device_t dev) { printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n"); struct resource *res = find_resource(dev, 0x10); if (!res) { printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); return; } void *bar0 = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n", (read32(bar0) >> 8), (read32(bar0) & 0xff)); printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", (read32(bar0 + 4) & 3)); printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); }
static void gma_func0_init(struct device *dev) { u32 reg32; /* IGD needs to be Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); /* Init graphics power management */ gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); struct northbridge_intel_gm45_config *conf = dev->chip_info; if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* PCI Init, will run VBIOS */ pci_dev_init(dev); } /* Post VBIOS init */ gma_pm_init_post_vbios(dev); if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { u32 physbase; struct resource *lfb_res; struct resource *pio_res; lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); physbase = pci_read_config32(dev, 0x5c) & ~0xf; if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base && lfb_res && lfb_res->base) { printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, pio_res->base, lfb_res->base); } /* Linux relies on VBT for panel info. */ generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE"); } }
static void sata_init(struct device *dev) { uint8_t byte; u8 *mmio; struct resource *res; u8 *mmio_base; int i; if(!(dev->path.pci.devfn & 7)) { // only set it in Func0 byte = pci_read_config8(dev, 0x78); byte |= (1<<7); pci_write_config8(dev, 0x78, byte); res = find_resource(dev, 0x24); mmio_base = res2mmio(res, 0, 3); write32(mmio_base + 0x10f0, 0x40000001); write32(mmio_base + 0x8c, 0x00ff2007); mdelay( 10 ); write32(mmio_base + 0x8c, 0x78592009); mdelay( 10 ); write32(mmio_base + 0x8c, 0x00082004); mdelay( 10 ); write32(mmio_base + 0x8c, 0x00002004); mdelay( 10 ); //init PHY printk(BIOS_DEBUG, "init PHY...\n"); for(i=0; i<4; i++) { mmio = (u8 *)(uintptr_t)(res->base + 0x100 * i); byte = read8(mmio + 0x40); printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte); if(byte & 0x4) {// bit 2 is set byte = read8(mmio+0x48); write8(mmio + 0x48, byte | 1); write8(mmio + 0x48, byte & (~1)); byte = read8(mmio + 0x40); printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); } } } }
static void usb2_init(struct device *dev) { u8 *base; struct resource *res; int i; u8 temp8; printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n"); //-------------- enable USB2.0 (SiS7002) ---------------------- i = 0; while (SiS_SiS7002_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]); temp8 &= SiS_SiS7002_init[i][1]; temp8 |= SiS_SiS7002_init[i][2]; pci_write_config8(dev, SiS_SiS7002_init[i][0], temp8); i++; }; res = find_resource(dev, 0x10); if (!res) return; base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "base = 0x%p\n", base); write32(base + 0x20, 0x2); //------------------------------------------------------------- #if DEBUG_USB2 printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); for (i=0;i<0xff;i+=4) { if ((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } printk(BIOS_DEBUG, "\n"); #endif printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n"); }
static void minihd_init(struct device *dev) { struct resource *res; u8 *base, reg32; int codec_mask, i; /* Find base address */ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); /* Set Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); /* Mini-HD configuration */ reg32 = read32(base + 0x100c); reg32 &= 0xfffc0000; reg32 |= 0x4; write32(base + 0x100c, reg32); reg32 = read32(base + 0x1010); reg32 &= 0xfffc0000; reg32 |= 0x4b; write32(base + 0x1010, reg32); /* Init the codec and write the verb table */ codec_mask = hda_codec_detect(base); if (codec_mask) { for (i = 3; i >= 0; i--) { if (codec_mask & (1 << i)) hda_codec_init(base, i, sizeof(minihd_verb_table), minihd_verb_table); } } }
static void nic_init(struct device *dev) { struct southbridge_amd_amd8111_config *conf; struct resource *resource; u8 *mmio; conf = dev->chip_info; resource = find_resource(dev, PCI_BASE_ADDRESS_0); mmio = res2mmio(resource, 0, 0); /* Hard Reset PHY */ printk(BIOS_DEBUG, "Resetting PHY... "); if (conf->phy_lowreset) { write32((mmio + CMD3), VAL0 | PHY_RST_POL | RESET_PHY); } else { write32((mmio + CMD3), VAL0 | RESET_PHY); } mdelay(15); write32((mmio + CMD3), RESET_PHY); printk(BIOS_DEBUG, "Done\n"); }
void azalia_audio_init(struct device *dev) { u8 *base; struct resource *res; u32 codec_mask; res = find_resource(dev, 0x10); if (!res) return; // NOTE this will break as soon as the azalia_audio get's a bar above // 4G. Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask); codecs_init(dev, base, codec_mask); } }
static void thermal_init(struct device *dev) { struct resource *res; u8 *base; printk(BIOS_DEBUG, "Thermal init start.\n"); res = find_resource(dev, 0x10); if (!res) return; base = res2mmio(res, 0, 0); write32(base + 4, 0x3a2b); write8(base + 0xe, 0x40); write16(base + 0x56, 0xffff); write16(base + 0x64, 0xffff); write16(base + 0x66, 0xffff); write16(base + 0x68, 0xfa); write8(base + 1, 0xb8); printk(BIOS_DEBUG, "Thermal init done.\n"); }
static void native_init(struct device *dev) { struct resource *lfb_res; struct resource *pio_res; u32 physbase; struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); struct northbridge_intel_x4x_config *conf = dev->chip_info; lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); physbase = pci_read_config32(dev, 0x5c) & ~0xf; if (gtt_res && gtt_res->base) { printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", gtt_res->base); intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, pio_res->base, lfb_res->base); } /* Linux relies on VBT for panel info. */ generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE"); }
/* Enable LTR Auto Mode for D21:F1-F6. */ static void serialio_d21_ltr(struct resource *bar0) { u32 reg; /* 1. Program BAR0 + 808h[2] = 0b */ reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0)); reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK; write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg); /* 2. Program BAR0 + 804h[1:0] = 00b */ reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0)); reg &= ~SIO_REG_PPR_RST_ASSERT; write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg); /* 3. Program BAR0 + 804h[1:0] = 11b */ reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0)); reg |= SIO_REG_PPR_RST_ASSERT; write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg); /* 4. Program BAR0 + 814h[31:0] = 00000000h */ write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int isa_bus; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); printk(BIOS_DEBUG, "%s: apic_id=0x%x\n", __func__, apicid_sb600); mptable_write_buses(mc, NULL, &isa_bus); /* I/O APICs: APIC ID Version State Address */ { device_t dev; dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 0)); if (dev) { struct resource *res; res = find_resource(dev, 0x74); smp_write_ioapic(mc, apicid_sb600, 0x20, res2mmio(res, 0, 0)); } } mptable_add_isa_interrupts(mc, isa_bus, apicid_sb600, 0); #define PCI_INT(bus, dev, fn, pin) \ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb600, (pin)) /* usb */ PCI_INT(0x0, 0x13, 0x0, 0x10); PCI_INT(0x0, 0x13, 0x1, 0x11); PCI_INT(0x0, 0x13, 0x2, 0x12); PCI_INT(0x0, 0x13, 0x3, 0x13); /* sata */ PCI_INT(0x0, 0x12, 0x1, 0x16); /* SMBus/ACPI */ PCI_INT(0x0, 0x14, 0x0, 0x10); /* IDE */ PCI_INT(0x0, 0x14, 0x1, 0x11); /* HDA */ PCI_INT(0x0, 0x14, 0x2, 0x12); /* LPC */ PCI_INT(0x0, 0x14, 0x3, 0x13); /* GFX ? */ PCI_INT(bus_rs690[1], 0x5, 0x0, 0x12); PCI_INT(bus_rs690[1], 0x5, 0x1, 0x13); /* PCIe slots */ PCI_INT(0x2, 0x00, 0x00, 0x10); PCI_INT(0x2, 0x00, 0x01, 0x11); PCI_INT(0x2, 0x00, 0x02, 0x12); PCI_INT(0x2, 0x00, 0x03, 0x13); /* PCIe slots */ PCI_INT(0x3, 0x00, 0x00, 0x11); PCI_INT(0x3, 0x00, 0x01, 0x12); PCI_INT(0x3, 0x00, 0x02, 0x13); PCI_INT(0x3, 0x00, 0x03, 0x10); /* PCIe slots */ PCI_INT(0x4, 0x00, 0x00, 0x12); PCI_INT(0x4, 0x00, 0x01, 0x13); PCI_INT(0x4, 0x00, 0x02, 0x10); PCI_INT(0x4, 0x00, 0x03, 0x11); /* PCIe slots */ PCI_INT(0x5, 0x00, 0x00, 0x13); PCI_INT(0x5, 0x00, 0x01, 0x10); PCI_INT(0x5, 0x00, 0x02, 0x11); PCI_INT(0x5, 0x00, 0x03, 0x12); /* onboard NIC ? */ PCI_INT(bus_sb600[1], 0x7, 0x0, 0x13); PCI_INT(bus_sb600[1], 0x7, 0x1, 0x10); PCI_INT(bus_sb600[1], 0x7, 0x2, 0x11); PCI_INT(bus_sb600[1], 0x7, 0x3, 0x12); /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, isa_bus); /* Compute the checksums */ return mptable_finalize(mc); }
void gtt_write(u32 reg, u32 data) { write32(res2mmio(gtt_res, reg, 0), data); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; struct mb_sysconf_t *m; unsigned sbdn; int i, j, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); sbdn = sysconf.sbdn; m = sysconf.mb; mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ { struct device *dev; struct resource *res; uint32_t dword; dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res2mmio(res, 0, 0)); } dword = 0x00000ab5; pci_write_config32(dev, 0x7c, dword); dword = 0x5ab0a500; pci_write_config32(dev, 0x80, dword); dword = 0xa000000b; pci_write_config32(dev, 0x84, dword); } } mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 1, 1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 0, m->apicid_mcp55, 0xb); /* 11 USB, OK */ smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 2, 1, m->apicid_mcp55, 0xa); /* 10 USB, OK */ smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/ smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 5, 2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/ smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[0], sbdn + 6, 1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/ smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 3, 0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/ smp_write_pci_intsrc(mc, mp_INT, m->bus_8132_2, 3, 1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/ for(j = 7;j >= 2; j--) { if(!m->bus_mcp55[j]) continue; for(i = 0; i < 4; i++) { smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[j], 0x00, i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } for(j = 0; j < 1; j++) for(i = 0; i < 4; i++) { smp_write_pci_intsrc(mc, mp_INT, m->bus_mcp55[1], 0x04+j, i, m->apicid_mcp55, 0x10 + (2+i+j)%4); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
u32 gtt_read(u32 reg) { return read32(res2mmio(gtt_res, reg, 0)); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; unsigned sbdn; int bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); sbdn = sysconf.sbdn; mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ { device_t dev; struct resource *res; dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x1, 0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_ck804, 0x11, res2mmio(res, 0, 0)); } /* Initialize interrupt mapping. */ /* LPC bridge PCI config registers: 0x7c:0x0000ffff - bitmap of masked pci irqs? - PIRQ[ABCD] possibly? 0x7c:0x00f00000 - sata at f8 - port 1 0x7c:0x0f000000 - sata at f7 - port 1 0x80:0xf0000000 - sata at f7 - port 0 0x80:0x0f000000 - sata at f8 - port 0 0x80:0x0000f000 - EHCI 0x84:0x00000f00 - NIC 0x84:0x0000000f - OHCI known values of nibbles: 0 - unrouted? 1 - irq 23 8 - irq 20 c - irq 12 d - irq 21 e - irq 14 f - irq 15 */ // Enable interrupts for commonly used devices (USB, SATA, etc.) pci_write_config32(dev, 0x7c, 0x0d800018); pci_write_config32(dev, 0x80, 0xd8002009); pci_write_config32(dev, 0x84, 0x00000001); } } mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0); // Onboard ck804 smbus smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804, 0xa); // Onboard ck804 USB 1.1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804, 0x15); // Onboard ck804 USB 2 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804, 0x14); // Onboard ck804 SATA 0 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804, 0x17); // Onboard ck804 SATA 1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804, 0x16); /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ mptable_lintsrc(mc, bus_ck804[0]); /* There is no extension information... */ /* Compute the checksums. */ return mptable_finalize(mc); }
static void *smp_write_config_table(void *v) { struct mp_config_table *mc; unsigned sbdn; int i, j, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); smp_write_processors(mc); get_bus_conf(); sbdn = sysconf.sbdn; mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ { device_t dev; struct resource *res; uint32_t dword; dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_1); if (res) { smp_write_ioapic(mc, apicid_mcp55, 0x11, res2mmio(res, 0, 0)); } dword = 0x43c6c643; pci_write_config32(dev, 0x7c, dword); dword = 0x81001a00; pci_write_config32(dev, 0x80, dword); dword = 0xd00012d2; pci_write_config32(dev, 0x84, dword); } } mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+1)<<2)|1, apicid_mcp55, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|0, apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+2)<<2)|1, apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+6)<<2)|1, apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|0, apicid_mcp55, 0x14); // 20 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|1, apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+5)<<2)|2, apicid_mcp55, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+8)<<2)|0, apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[0], ((sbdn+9)<<2)|0, apicid_mcp55, 0x15); // 21 for(j=7; j>=2; j--) { if(!bus_mcp55[j]) continue; for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[j], (0x00<<2)|i, apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); } } for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_mcp55[1], (0x04<<2)|i, apicid_mcp55, 0x10 + (0+i)%4); } if(bus_pcix[0]) { for(i=0;i<2;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[2], (4<<2)|i, apicid_mcp55, 0x10 + (0+i+4-sbdn%4)%4); //16, 17 } for(i=0;i<4;i++) { smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcix[1], (4<<2)|i, apicid_mcp55, 0x10 + (2+i+4-sbdn%4)%4); // 18, 19, 16, 17 } } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ mptable_lintsrc(mc, bus_isa); /* There is no extension information... */ /* Compute the checksums */ return mptable_finalize(mc); }
static void nic_init(struct device *dev) { u32 dword, old, mac_h = 0, mac_l = 0; int eeprom_valid = 0; struct southbridge_nvidia_ck804_config *conf; static u32 nic_index = 0; u8 *base; struct resource *res; res = find_resource(dev, 0x10); base = res2mmio(res, 0, 0); #define NvRegPhyInterface 0xC0 #define PHY_RGMII 0x10000000 write32(base + NvRegPhyInterface, PHY_RGMII); old = dword = pci_read_config32(dev, 0x30); dword &= ~(0xf); dword |= 0xf; if (old != dword) pci_write_config32(dev, 0x30, dword); conf = dev->chip_info; if (conf->mac_eeprom_smbus != 0) { /* Read MAC address from EEPROM at first. */ struct device *dev_eeprom; dev_eeprom = dev_find_slot_on_smbus(conf->mac_eeprom_smbus, conf->mac_eeprom_addr); if (dev_eeprom) { /* If that is valid we will use that. */ unsigned char dat[6]; int i, status; for (i = 0; i < 6; i++) { status = smbus_read_byte(dev_eeprom, i); if (status < 0) break; dat[i] = status & 0xff; } if (status >= 0) { mac_l = 0; for (i = 3; i >= 0; i--) { mac_l <<= 8; mac_l += dat[i]; } if (mac_l != 0xffffffff) { mac_l += nic_index; mac_h = 0; for (i = 5; i >= 4; i--) { mac_h <<= 8; mac_h += dat[i]; } eeprom_valid = 1; } } } } /* If that is invalid we will read that from romstrap. */ if (!eeprom_valid) { u32 *mac_pos; mac_pos = (u32 *)0xffffffd0; /* See romstrap.inc and romstrap.ld. */ mac_l = read32(mac_pos) + nic_index; mac_h = read32(mac_pos + 1); } #if 1 /* Set that into NIC MMIO. */ #define NvRegMacAddrA 0xA8 #define NvRegMacAddrB 0xAC write32(base + NvRegMacAddrA, mac_l); write32(base + NvRegMacAddrB, mac_h); #else /* Set that into NIC. */ pci_write_config32(dev, 0xa8, mac_l); pci_write_config32(dev, 0xac, mac_h); #endif nic_index++; }
static void gtt_write(unsigned long reg, unsigned long data) { write32(res2mmio(gtt_res, reg, 0), data); }