static int bcm6358_usbh_probe(struct udevice *dev) { struct bcm6358_usbh_priv *priv = dev_get_priv(dev); struct reset_ctl rst_ctl; int ret; priv->regs = dev_remap_addr(dev); if (!priv->regs) return -EINVAL; /* perform reset */ ret = reset_get_by_index(dev, 0, &rst_ctl); if (ret < 0) return ret; ret = reset_deassert(&rst_ctl); if (ret < 0) return ret; ret = reset_free(&rst_ctl); if (ret < 0) return ret; return 0; }
int reset_get_by_name(struct udevice *dev, const char *name, struct reset_ctl *reset_ctl) { int index; debug("%s(dev=%p, name=%s, reset_ctl=%p)\n", __func__, dev, name, reset_ctl); index = fdt_find_string(gd->fdt_blob, dev->of_offset, "reset-names", name); if (index < 0) { debug("fdt_find_string() failed: %d\n", index); return index; } return reset_get_by_index(dev, index, reset_ctl); }
static int ohci_usb_probe(struct udevice *dev) { struct ohci_regs *regs = (struct ohci_regs *)devfdt_get_addr(dev); struct generic_ohci *priv = dev_get_priv(dev); int i, err, ret, clock_nb, reset_nb; err = 0; priv->clock_count = 0; clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); if (clock_nb > 0) { priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), GFP_KERNEL); if (!priv->clocks) return -ENOMEM; for (i = 0; i < clock_nb; i++) { err = clk_get_by_index(dev, i, &priv->clocks[i]); if (err < 0) break; err = clk_enable(&priv->clocks[i]); if (err) { pr_err("failed to enable clock %d\n", i); clk_free(&priv->clocks[i]); goto clk_err; } priv->clock_count++; } } else if (clock_nb != -ENOENT) { pr_err("failed to get clock phandle(%d)\n", clock_nb); return clock_nb; } priv->reset_count = 0; reset_nb = dev_count_phandle_with_args(dev, "resets", "#reset-cells"); if (reset_nb > 0) { priv->resets = devm_kcalloc(dev, reset_nb, sizeof(struct reset_ctl), GFP_KERNEL); if (!priv->resets) return -ENOMEM; for (i = 0; i < reset_nb; i++) { err = reset_get_by_index(dev, i, &priv->resets[i]); if (err < 0) break; err = reset_deassert(&priv->resets[i]); if (err) { pr_err("failed to deassert reset %d\n", i); reset_free(&priv->resets[i]); goto reset_err; } priv->reset_count++; } } else if (reset_nb != -ENOENT) { pr_err("failed to get reset phandle(%d)\n", reset_nb); goto clk_err; } err = generic_phy_get_by_index(dev, 0, &priv->phy); if (err) { if (err != -ENOENT) { pr_err("failed to get usb phy\n"); goto reset_err; } } else { err = generic_phy_init(&priv->phy); if (err) { pr_err("failed to init usb phy\n"); goto reset_err; } } err = ohci_register(dev, regs); if (err) goto phy_err; return 0; phy_err: if (generic_phy_valid(&priv->phy)) { ret = generic_phy_exit(&priv->phy); if (ret) pr_err("failed to release phy\n"); } reset_err: ret = reset_release_all(priv->resets, priv->reset_count); if (ret) pr_err("failed to assert all resets\n"); clk_err: ret = clk_release_all(priv->clocks, priv->clock_count); if (ret) pr_err("failed to disable all clocks\n"); return err; }
static int stm32_sdmmc2_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct stm32_sdmmc2_plat *plat = dev_get_platdata(dev); struct stm32_sdmmc2_priv *priv = dev_get_priv(dev); struct mmc_config *cfg = &plat->cfg; int ret; priv->base = dev_read_addr(dev); if (priv->base == FDT_ADDR_T_NONE) return -EINVAL; if (dev_read_bool(dev, "st,negedge")) priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE; if (dev_read_bool(dev, "st,dirpol")) priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL; ret = clk_get_by_index(dev, 0, &priv->clk); if (ret) return ret; ret = clk_enable(&priv->clk); if (ret) goto clk_free; ret = reset_get_by_index(dev, 0, &priv->reset_ctl); if (ret) goto clk_disable; gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN); cfg->f_min = 400000; cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000); cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; cfg->name = "STM32 SDMMC2"; cfg->host_caps = 0; if (cfg->f_max > 25000000) cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; switch (dev_read_u32_default(dev, "bus-width", 1)) { case 8: cfg->host_caps |= MMC_MODE_8BIT; case 4: cfg->host_caps |= MMC_MODE_4BIT; break; case 1: break; default: pr_err("invalid \"bus-width\" property, force to 1\n"); } upriv->mmc = &plat->mmc; return 0; clk_disable: clk_disable(&priv->clk); clk_free: clk_free(&priv->clk); return ret; }
static int ehci_usb_probe(struct udevice *dev) { struct generic_ehci *priv = dev_get_priv(dev); struct ehci_hccr *hccr; struct ehci_hcor *hcor; int i, err, ret, clock_nb, reset_nb; err = 0; priv->clock_count = 0; clock_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "clocks", "#clock-cells"); if (clock_nb > 0) { priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), GFP_KERNEL); if (!priv->clocks) return -ENOMEM; for (i = 0; i < clock_nb; i++) { err = clk_get_by_index(dev, i, &priv->clocks[i]); if (err < 0) break; err = clk_enable(&priv->clocks[i]); if (err) { pr_err("failed to enable clock %d\n", i); clk_free(&priv->clocks[i]); goto clk_err; } priv->clock_count++; } } else { if (clock_nb != -ENOENT) { pr_err("failed to get clock phandle(%d)\n", clock_nb); return clock_nb; } } priv->reset_count = 0; reset_nb = ofnode_count_phandle_with_args(dev_ofnode(dev), "resets", "#reset-cells"); if (reset_nb > 0) { priv->resets = devm_kcalloc(dev, reset_nb, sizeof(struct reset_ctl), GFP_KERNEL); if (!priv->resets) return -ENOMEM; for (i = 0; i < reset_nb; i++) { err = reset_get_by_index(dev, i, &priv->resets[i]); if (err < 0) break; if (reset_deassert(&priv->resets[i])) { pr_err("failed to deassert reset %d\n", i); reset_free(&priv->resets[i]); goto reset_err; } priv->reset_count++; } } else { if (reset_nb != -ENOENT) { pr_err("failed to get reset phandle(%d)\n", reset_nb); goto clk_err; } } err = generic_phy_get_by_index(dev, 0, &priv->phy); if (err) { if (err != -ENOENT) { pr_err("failed to get usb phy\n"); goto reset_err; } } else { err = generic_phy_init(&priv->phy); if (err) { pr_err("failed to init usb phy\n"); goto reset_err; } } hccr = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE); hcor = (struct ehci_hcor *)((uintptr_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); err = ehci_register(dev, hccr, hcor, NULL, 0, USB_INIT_HOST); if (err) goto phy_err; return 0; phy_err: if (generic_phy_valid(&priv->phy)) { ret = generic_phy_exit(&priv->phy); if (ret) pr_err("failed to release phy\n"); } reset_err: ret = reset_release_all(priv->resets, priv->reset_count); if (ret) pr_err("failed to assert all resets\n"); clk_err: ret = clk_release_all(priv->clocks, priv->clock_count); if (ret) pr_err("failed to disable all clocks\n"); return err; }
static int stm32_qspi_probe(struct udevice *bus) { struct stm32_qspi_priv *priv = dev_get_priv(bus); struct resource res; struct clk clk; struct reset_ctl reset_ctl; int ret; ret = dev_read_resource_byname(bus, "qspi", &res); if (ret) { dev_err(bus, "can't get regs base addresses(ret = %d)!\n", ret); return ret; } priv->regs = (struct stm32_qspi_regs *)res.start; ret = dev_read_resource_byname(bus, "qspi_mm", &res); if (ret) { dev_err(bus, "can't get mmap base address(ret = %d)!\n", ret); return ret; } priv->mm_base = (void __iomem *)res.start; priv->mm_size = resource_size(&res); if (priv->mm_size > STM32_QSPI_MAX_MMAP_SZ) return -EINVAL; debug("%s: regs=<0x%p> mapped=<0x%p> mapped_size=<0x%lx>\n", __func__, priv->regs, priv->mm_base, priv->mm_size); ret = clk_get_by_index(bus, 0, &clk); if (ret < 0) return ret; ret = clk_enable(&clk); if (ret) { dev_err(bus, "failed to enable clock\n"); return ret; } priv->clock_rate = clk_get_rate(&clk); if (priv->clock_rate < 0) { clk_disable(&clk); return priv->clock_rate; } ret = reset_get_by_index(bus, 0, &reset_ctl); if (ret) { if (ret != -ENOENT) { dev_err(bus, "failed to get reset\n"); clk_disable(&clk); return ret; } } else { /* Reset QSPI controller */ reset_assert(&reset_ctl); udelay(2); reset_deassert(&reset_ctl); } priv->cs_used = -1; setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT); /* Set dcr fsize to max address */ setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_FSIZE_MASK << STM32_QSPI_DCR_FSIZE_SHIFT); return 0; }