static void mdss_vbif_setup() { int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); uint32_t mdp_hw_rev = readl(MDP_HW_REV); /* TZ returns an errornous ret val even if the VBIF registers were * successfully unlocked. Ignore TZ return value till it's fixed */ if (!access_secure || 1) { dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); /* Force VBIF Clocks on */ writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); if (mdp_hw_rev == MDSS_MDP_HW_REV_100 || mdp_hw_rev >= MDSS_MDP_HW_REV_102) { /* Configure DDR burst length */ writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); } else if (mdp_hw_rev >= MDSS_MDP_HW_REV_101) { writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); writel(0x00000003, VBIF_VBIF_DDR_ARB_CTRL); } } }
static void mdss_vbif_setup() { int access_secure = restore_secure_cfg(SECURE_DEVICE_MDSS); uint32_t mdp_hw_rev = readl(MDP_HW_REV); if (!access_secure) { dprintf(SPEW, "MDSS VBIF registers unlocked by TZ.\n"); /* Force VBIF Clocks on, not needed for 8084 */ if ((mdp_hw_rev < MDSS_MDP_HW_REV_103) || (mdp_hw_rev == MDSS_MDP_HW_REV_106)) writel(0x1, VBIF_VBIF_DDR_FORCE_CLK_ON); /* * Following configuration is needed because on some versions, * recommended reset values are not stored. */ if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_100)) { writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); writel(0x00000030, VBIF_VBIF_DDR_ARB_CTRL ); writel(0x00000001, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); writel(0x00000FFF, VBIF_VBIF_DDR_OUT_AOOO_AXI_EN); writel(0x0FFF0FFF, VBIF_VBIF_DDR_OUT_AX_AOOO); writel(0x22222222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF0); writel(0x00002222, VBIF_VBIF_DDR_AXI_AMEMTYPE_CONF1); } else if (MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_101) || MDSS_IS_MAJOR_MINOR_MATCHING(mdp_hw_rev, MDSS_MDP_HW_REV_106)) { writel(0x00000707, VBIF_VBIF_DDR_OUT_MAX_BURST); writel(0x00000003, VBIF_VBIF_DDR_RND_RBN_QOS_ARB); } } }
int target_edp_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) { uint32_t ret; dprintf(SPEW, "%s: target_panel_clock\n", __func__); if (enable) { mdp_gdsc_ctrl(enable); mmss_bus_clock_enable(); mdp_clock_enable(); ret = restore_secure_cfg(SECURE_DEVICE_MDSS); if (ret) { dprintf(CRITICAL, "%s: Failed to restore MDP security configs", __func__); mdp_clock_disable(); mmss_bus_clock_disable(); mdp_gdsc_ctrl(0); return ret; } edp_clk_enable(); } else if(!target_cont_splash_screen()) { /* Disable clocks if continuous splash off */ edp_clk_disable(); mdp_clock_disable(); mmss_bus_clock_disable(); mdp_gdsc_ctrl(enable); } return NO_ERROR; }
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) { int32_t ret = 0; struct mdss_dsi_pll_config *pll_data; dprintf(SPEW, "target_panel_clock\n"); pll_data = pinfo->mipi.dsi_pll_config; pll_data->vco_delay = VCO_DELAY_USEC; if (enable) { mdp_gdsc_ctrl(enable); mdss_bus_clocks_enable(); mdp_clock_enable(); ret = restore_secure_cfg(SECURE_DEVICE_MDSS); if (ret) { dprintf(CRITICAL, "%s: Failed to restore MDP security configs", __func__); mdp_clock_disable(); mdss_bus_clocks_disable(); mdp_gdsc_ctrl(0); return ret; } mdss_dsi_uniphy_pll_sw_reset_8916(DSI0_PLL_BASE); mdss_dsi_auto_pll_config(DSI0_PLL_BASE, MIPI_DSI0_BASE, pll_data); if (!dsi_pll_enable_seq_8916(DSI0_PLL_BASE)) dprintf(CRITICAL, "Not able to enable the pll\n"); gcc_dsi_clocks_enable(pinfo->mipi.dual_dsi, pll_data->pclk_m, pll_data->pclk_n, pll_data->pclk_d); } else if(!target_cont_splash_screen()) { gcc_dsi_clocks_disable(pinfo->mipi.dual_dsi); mdp_clock_disable(); mdss_bus_clocks_disable(); mdp_gdsc_ctrl(enable); } return 0; }
int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) { int32_t ret; struct mdss_dsi_pll_config *pll_data; dprintf(SPEW, "target_panel_clock\n"); pll_data = pinfo->mipi.dsi_pll_config; if (enable) { mdp_gdsc_ctrl(enable); mmss_bus_clocks_enable(); mdp_clock_enable(); ret = restore_secure_cfg(SECURE_DEVICE_MDSS); if (ret) { dprintf(CRITICAL, "%s: Failed to restore MDP security configs", __func__); mdp_clock_disable(); mmss_bus_clocks_disable(); mdp_gdsc_ctrl(0); return ret; } mdss_dsi_auto_pll_config(DSI0_PLL_BASE, MIPI_DSI0_BASE, pll_data); dsi_pll_enable_seq(DSI0_PLL_BASE); mmss_dsi_clocks_enable(pll_data->pclk_m, pll_data->pclk_n, pll_data->pclk_d); } else if(!target_cont_splash_screen()) { mmss_dsi_clocks_disable(); mdp_clock_disable(); mmss_bus_clocks_disable(); mdp_gdsc_ctrl(enable); } return 0; }
int target_backlight_ctrl(struct backlight *bl, uint8_t enable) { struct pm8x41_gpio pwmgpio_param = { .direction = PM_GPIO_DIR_OUT, .function = PM_GPIO_FUNC_1, .vin_sel = 2, /* VIN_2 */ .pull = PM_GPIO_PULL_UP_1_5 | PM_GPIO_PULLDOWN_10, .output_buffer = PM_GPIO_OUT_CMOS, .out_strength = 0x03, }; if (enable) { pm8x41_gpio_config(pwm_gpio.pin_id, &pwmgpio_param); /* lpg channel 3 */ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x41, 0x33); /* LPG_PWM_SIZE_CLK, */ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x42, 0x01); /* LPG_PWM_FREQ_PREDIV */ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x43, 0x20); /* LPG_PWM_TYPE_CONFIG */ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x44, 0xcc); /* LPG_VALUE_LSB */ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x45, 0x00); /* LPG_VALUE_MSB */ pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0xe4); /* LPG_ENABLE_CONTROL */ } else { pm8x41_lpg_write(PWM_BL_LPG_CHAN_ID, 0x46, 0x0); /* LPG_ENABLE_CONTROL */ } return NO_ERROR; } int target_panel_clock(uint8_t enable, struct msm_panel_info *pinfo) { uint32_t ret; struct mdss_dsi_pll_config *pll_data; uint32_t dual_dsi = pinfo->mipi.dual_dsi; dprintf(SPEW, "target_panel_clock\n"); pll_data = pinfo->mipi.dsi_pll_config; if (enable) { mdp_gdsc_ctrl(enable); mmss_bus_clock_enable(); mdp_clock_enable(); ret = restore_secure_cfg(SECURE_DEVICE_MDSS); if (ret) { dprintf(CRITICAL, "%s: Failed to restore MDP security configs", __func__); mdp_clock_disable(); mmss_bus_clock_disable(); mdp_gdsc_ctrl(0); return ret; } mdss_dsi_auto_pll_config(DSI0_PLL_BASE, MIPI_DSI0_BASE, pll_data); dsi_pll_enable_seq(DSI0_PLL_BASE); mmss_dsi_clock_enable(DSI0_PHY_PLL_OUT, dual_dsi, pll_data->pclk_m, pll_data->pclk_n, pll_data->pclk_d); } else if(!target_cont_splash_screen()) { /* Disable clocks if continuous splash off */ mmss_dsi_clock_disable(dual_dsi); mdp_clock_disable(); mmss_bus_clock_disable(); mdp_gdsc_ctrl(enable); } return NO_ERROR; }