void riot1_store(drive_context_t *ctxptr, WORD addr, BYTE data)
{
riotcore_store(ctxptr->riot1, addr, data);
}
void REGPARM3 riotcore_store(riot_context_t *riot_context, WORD addr, BYTE byte)
{
CLOCK rclk;
if (riot_context->rmw_flag) {
(*(riot_context->clk_ptr))--;
riot_context->rmw_flag = 0;
riotcore_store(riot_context, addr, riot_context->last_read);
(*(riot_context->clk_ptr))++;
}
rclk = *(riot_context->clk_ptr) - 1; /* stores have a one-cylce offset */
addr &= 0x1f;
/* manage the weird addressing schemes */
if ((addr & 0x04) == 0) { /* I/O */
addr &= 3;
switch (addr) {
case 0: /* ORA */
case 1: /* DDRA */
(riot_context->riot_io)[addr] = byte;
byte = (riot_context->riot_io)[0] | ~(riot_context->riot_io)[1];
riot_context->store_pra(riot_context, byte);
riot_context->old_pa = byte;
break;
case 2: /* ORB */
case 3: /* DDRB */
(riot_context->riot_io)[addr] = byte;
byte = (riot_context->riot_io)[2] | ~(riot_context->riot_io)[3];
riot_context->store_prb(riot_context, byte);
riot_context->old_pb = byte;
break;
}
} else
if ((addr & 0x14) == 0x14) { /* set timer */
int newirq = riot_context->r_irqfl & 0x7f;
/*
log_warning(riot_context->log,
"write timer %02x@%d not yet implemented\n",
byte, addr);
*/
riot_context->r_divider = divider[addr & 3];
riot_context->r_write_clk = rclk + 1;
riot_context->r_N = byte;
riot_context->r_irqen = (addr & 8);
if (byte) {
(riot_context->r_N)--;
if (riot_context->r_irqen) {
alarm_set(riot_context->alarm, riot_context->r_write_clk
+ riot_context->r_N * riot_context->r_divider);
}
} else {
/* setup IRQ? */
riot_context->r_N = 255;
riot_context->r_divider = 1;
if (riot_context->r_irqen) {
newirq |= 0x80;
}
}
update_irq(riot_context, (BYTE)(newirq));
if (!(riot_context->r_irqen)) {
alarm_unset(riot_context->alarm);
}
} else
if ((addr & 0x14) == 0x04) { /* set edge detect control */
/*
log_message(riot_context->log, "edge control %02x@%d\n", byte, addr);
*/
riot_context->r_edgectrl = addr & 3;
update_irq(riot_context, riot_context->r_irqfl);
}
}
