static int rk3036_clk_probe(struct udevice *dev)
{
struct rk3036_clk_priv *priv = dev_get_priv(dev);
rkclk_init(priv->cru);
return 0;
}
void bootblock_soc_init(void)
{
rkclk_init();
mmu_init();
/* Start with a clean slate. */
mmu_config_range(0, 4096, DCACHE_OFF);
/* SRAM is tightly wedged between registers, need to use subtables. Map
* write-through as equivalent for non-cacheable without XN on A17. */
mmu_config_range_kb((uintptr_t)_sram/KiB,
_sram_size/KiB, DCACHE_WRITETHROUGH);
dcache_mmu_enable();
rkclk_configure_crypto(148500*KHz);
}
void bootblock_soc_init(void)
{
rkclk_init();
rkclk_configure_cpu(APLL_600_MHZ, false);
/* all ddr range non-secure */
write32(&rk3399_pmusgrf->ddr_rgn_con[16], 0xff << 16 | 0);
/* tzma_rosize = 0, all sram non-secure */
write32(&rk3399_pmusgrf->soc_con4, 0x3ff << 16 | 0);
/* emmc master secure */
write32(&rk3399_pmusgrf->soc_con7, 1 << 23 | 1 << 24 | 0 << 8 | 0 << 7);
/* glb_slv_secure_bypass */
write32(&rk3399_pmusgrf->pmu_slv_con0, 1 << 16 | 1);
rockchip_mmu_init();
}
