void mainboard_romstage_entry(struct romstage_params *rp) { struct cbfs_file *spd_file; void *spd_content; int dual_channel = 0; struct mrc_params mp = { .mainboard = { .dram_type = DRAM_DDR3L, .dram_info_location = DRAM_INFO_SPD_MEM, .weaker_odt_settings = 1, }, }; spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); if (!spd_file) die("SPD data not found."); spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file), ntohl(spd_file->len) / SPD_SIZE, &dual_channel); mp.mainboard.dram_data[0] = spd_content; if (dual_channel) mp.mainboard.dram_data[1] = spd_content; rp->mrc_params = ∓ romstage_common(rp); }
void mainboard_romstage_entry(struct romstage_params *rp) { struct pei_data pei_data; post_code(0x31); if (rp->power_state->prev_sleep_state != SLEEP_STATE_S3) google_chromeec_kbbacklight(100); printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version()); /* Ensure the EC and PD are in the right mode for recovery */ google_chromeec_early_init(); /* Initialize GPIOs */ init_gpios(mainboard_gpio_config); /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; /* Initalize memory */ romstage_common(rp); /* Bring SSD out of reset */ set_gpio(SAMUS_GPIO_SSD_RESET_L, GPIO_OUT_HIGH); /* * Enable PP3300_AUTOBAHN_EN after initial GPIO setup * to prevent possible brownout. */ set_gpio(SAMUS_GPIO_PP3300_AUTOBAHN_EN, GPIO_OUT_HIGH); }
void mainboard_romstage_entry(struct romstage_params *rp) { void *spd_content; int dual_channel = 0; void *spd_file; size_t spd_fsize; struct mrc_params mp = { .mainboard = { .dram_type = DRAM_DDR3L, .dram_info_location = DRAM_INFO_SPD_MEM, .weaker_odt_settings = 1, }, }; spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize); if (!spd_file) die("SPD data not found."); /* Both channels are always present. */ spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, &dual_channel); mp.mainboard.dram_data[0] = spd_content; if (dual_channel) mp.mainboard.dram_data[1] = spd_content; rp->mrc_params = ∓ romstage_common(rp); }
void mainboard_romstage_entry(struct romstage_params *params) { post_code(0x31); /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); romstage_common(params); }
void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, .system_type = 1, /* desktop/server */ .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ec_present = 0, .dimm_channel0_disabled = 2, /* Disable DIMM 1 on channel 0. */ .dimm_channel1_disabled = 2, /* Disable DIMM 1 on channel 1. */ .max_ddr3_freq = 1600, .usb2_ports = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, { 0x0040, 1, 0, USB_PORT_BACK_PANEL }, { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, { 0x0040, 1, 2, USB_PORT_BACK_PANEL }, { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, { 0x0040, 1, 4, USB_PORT_BACK_PANEL }, { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, { 0x0040, 1, 5, USB_PORT_BACK_PANEL }, { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, { 0x0040, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP }, }, .usb3_ports = { /* Enable, OCn# */ { 1, 0 }, { 1, 0 }, { 0, USB_OC_PIN_SKIP }, { 0, USB_OC_PIN_SKIP }, { 0, USB_OC_PIN_SKIP }, { 0, USB_OC_PIN_SKIP }, }, }; struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .bist = bist, }; romstage_common(&romstage_params); }
void mainboard_romstage_entry(struct romstage_params *params) { /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data); /* Initliaze memory */ romstage_common(params); }
/* Board initialization before and after RAM is enabled */ __attribute__((weak)) void mainboard_romstage_entry( struct romstage_params *params) { post_code(0x31); /* Initliaze memory */ romstage_common(params); }
void mainboard_romstage_entry(struct romstage_params *rp) { struct mrc_params mp = { .mainboard = { .dram_type = DRAM_DDR3L, .dram_info_location = DRAM_INFO_SPD_SMBUS, .spd_addrs = { 0xa0, 0xa2 }, }, }; rp->mrc_params = ∓ romstage_common(rp); }
void mainboard_romstage_entry(struct romstage_params *params) { /* Ensure the EC and PD are in the right mode for recovery */ google_chromeec_early_init(); early_config_gpio(); /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data); /* Initliaze memory */ romstage_common(params); }
void mainboard_romstage_entry(struct romstage_params *rp) { struct pei_data pei_data; /* Initialize GPIOs */ init_gpios(mainboard_gpio_config); /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); rp->pei_data = &pei_data; /* Initialize memory */ romstage_common(rp); }
void mainboard_romstage_entry(struct romstage_params *params) { /* Ensure the EC and PD are in the right mode for recovery */ google_chromeec_early_init(); /* Turn on keyboard backlight to indicate we are booting */ if (params->power_state->prev_sleep_state != SLEEP_STATE_S3) google_chromeec_kbbacklight(100); early_config_gpio(); /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data); /* Initliaze memory */ romstage_common(params); }
void mainboard_romstage_entry(struct romstage_params *rp) { struct pei_data pei_data; post_code(0x32); /* Initialize GPIOs */ init_gpios(mainboard_gpio_config); /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; /* Call into the real romstage main with this board's attributes. */ romstage_common(rp); if (IS_ENABLED(CONFIG_CHROMEOS)) save_chromeos_gpios(); }
void mainboard_romstage_entry(struct romstage_params *params) { #ifdef EC_ENABLE_KEYBOARD_BACKLIGHT /* Turn on keyboard backlight to indicate we are booting */ if (params->power_state->prev_sleep_state != ACPI_S3) google_chromeec_kbbacklight(25); #endif /* Get SPD index */ gpio_t spd_gpios[] = { GPIO_MEM_CONFIG_0, GPIO_MEM_CONFIG_1, GPIO_MEM_CONFIG_2, GPIO_MEM_CONFIG_3, }; params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data); /* Initialize memory */ romstage_common(params); }
void mainboard_romstage_entry(struct romstage_params *params) { /* PCH_MEM_CFG[3:0] */ gpio_t spd_gpios[] = { GPIO_MEM_CONFIG_0, GPIO_MEM_CONFIG_1, GPIO_MEM_CONFIG_2, GPIO_MEM_CONFIG_3, }; /* Ensure the EC and PD are in the right mode for recovery */ google_chromeec_early_init(); early_config_gpio(); params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data); /* Initliaze memory */ romstage_common(params); }
void mainboard_romstage_entry(struct romstage_params *rp) { struct pei_data pei_data; post_code(0x32); /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init(); /* Initialize GPIOs */ init_gpios(mainboard_gpio_config); /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; /* Call into the real romstage main with this board's attributes. */ romstage_common(rp); /* Do variant-specific (read: Samus) init */ variant_romstage_entry(rp); }
void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = DEFAULT_MCHBAR, .dmibar = DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = DEFAULT_PCIEXBAR, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, .system_type = 0, // 0 Mobile, 1 Desktop/Server .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, .ec_present = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel .dimm_channel0_disabled = 0, .dimm_channel1_disabled = 0, .max_ddr3_freq = 1600, .usb2_ports = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ USB_PORT_BACK_PANEL }, { 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */ USB_PORT_BACK_PANEL }, { 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */ USB_PORT_FLEX }, { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */ USB_PORT_DOCK }, { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */ USB_PORT_MINI_PCIE }, { 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */ USB_PORT_FLEX }, { 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */ USB_PORT_FRONT_PANEL }, { 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */ USB_PORT_FRONT_PANEL }, { 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */ USB_PORT_FRONT_PANEL }, { 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */ USB_PORT_FRONT_PANEL }, { 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */ USB_PORT_FRONT_PANEL }, { 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */ USB_PORT_FRONT_PANEL }, { 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */ USB_PORT_FRONT_PANEL }, { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */ USB_PORT_FRONT_PANEL }, }, .usb3_ports = { /* Enable, OCn# */ { 1, 0 }, /* P1; */ { 1, 0 }, /* P2; */ { 1, 0 }, /* P3; */ { 1, 0 }, /* P4; */ { 1, 0 }, /* P6; */ { 1, 0 }, /* P6; */ }, }; struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .bist = bist, .copy_spd = NULL, }; /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); }
void variant_romstage_entry(unsigned long bist) { struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, .system_type = 5, /* ULT */ .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, .ec_present = 1, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, .max_ddr3_freq = 1600, .usb_xhci_on_resume = 1, .usb2_ports = { /* Length, Enable, OCn#, Location */ { 0x0040, 1, 0, /* P0: Port A, CN10 */ USB_PORT_BACK_PANEL }, { 0x0040, 1, 2, /* P1: Port B, CN11 */ USB_PORT_BACK_PANEL }, { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ USB_PORT_INTERNAL }, { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ USB_PORT_MINI_PCIE }, { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ USB_PORT_INTERNAL }, { 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */ USB_PORT_SKIP }, { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ USB_PORT_INTERNAL }, { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ USB_PORT_SKIP }, }, .usb3_ports = { /* Enable, OCn# */ { 1, 0 }, /* P1; Port A, CN10 */ { 1, 2 }, /* P2; Port B, CN11 */ { 0, USB_OC_PIN_SKIP }, /* P3; */ { 0, USB_OC_PIN_SKIP }, /* P4; */ }, }; struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .bist = bist, .copy_spd = copy_spd, }; /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); }
void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { .pei_version = PEI_VERSION, .mchbar = (uintptr_t)DEFAULT_MCHBAR, .dmibar = (uintptr_t)DEFAULT_DMIBAR, .epbar = DEFAULT_EPBAR, .pciexbar = DEFAULT_PCIEXBAR, .smbusbar = SMBUS_IO_BASE, .wdbbar = 0x4000000, .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, .system_type = 5, /* ULT */ .tseg_size = CONFIG_SMM_TSEG_SIZE, .spd_addresses = { 0xa0, 0x00, 0xa4, 0x00 }, .ec_present = 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel .dimm_channel0_disabled = 2, .dimm_channel1_disabled = 2, // Enable 2x refresh mode .ddr_refresh_2x = 1, .dq_pins_interleaved = 1, .max_ddr3_freq = 1600, .usb_xhci_on_resume = 1, .usb2_ports = { /* Length, Enable, OCn#, Location */ { 0x0064, 1, 0, /* P0: VP8 */ USB_PORT_MINI_PCIE }, { 0x0040, 1, 0, /* P1: Port A, CN22 */ USB_PORT_INTERNAL }, { 0x0040, 1, 1, /* P2: Port B, CN23 */ USB_PORT_INTERNAL }, { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: WLAN */ USB_PORT_INTERNAL }, { 0x0040, 1, 2, /* P4: Port C, CN25 */ USB_PORT_INTERNAL }, { 0x0040, 1, 2, /* P5: Port D, CN25 */ USB_PORT_INTERNAL }, { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: Card Reader */ USB_PORT_INTERNAL }, { 0x0000, 0, 0, /* P7: N/C */ USB_PORT_SKIP }, }, .usb3_ports = { /* Enable, OCn# */ { 1, 0 }, /* P1; CN22 */ { 1, 1 }, /* P2; CN23 */ { 1, 2 }, /* P3; CN25 */ { 1, 2 }, /* P4; CN25 */ }, }; struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, .rcba_config = &rcba_config[0], .bist = bist, }; /* Early SuperIO setup */ ite_kill_watchdog(IT8772F_GPIO_DEV); it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV); pch_enable_lpc(); ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); /* Turn on Power LED GP22 for Tricky */ it8772f_gpio_led(IT8772F_GPIO_DEV, 2 /* set */, 0xF7 /* select */, 0x04 /* polarity: inverting */, 0x00 /* 0=pulldown */, 0x04 /* output */, 0x04 /* 1=Simple IO function */, SIO_GPIO_BLINK_GPIO22, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); /* Call into the real romstage main with this board's attributes. */ romstage_common(&romstage_params); }