static int ehci_obio_detach(device_t self) { ehci_softc_t *sc = device_get_softc(self); device_t bdev; int err; if (sc->sc_bus.bdev) { bdev = sc->sc_bus.bdev; device_detach(bdev); device_delete_child(self, bdev); } /* during module unload there are lots of children leftover */ device_delete_children(self); if (sc->sc_irq_res && sc->sc_intr_hdl) { /* * only call ehci_detach() after ehci_init() */ ehci_detach(sc); /* Stop EHCI clock */ rt305x_sysctl_set(SYSCTL_CLKCFG1, rt305x_sysctl_get(SYSCTL_CLKCFG1) & ~(SYSCTL_CLKCFG1_UPHY0_CLK_EN #ifdef MT7620 | SYSCTL_CLKCFG1_UPHY1_CLK_EN #endif )); err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); if (err) device_printf(self, "Could not tear down irq, %d\n", err); sc->sc_intr_hdl = NULL; } if (sc->sc_irq_res) { bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res); sc->sc_irq_res = NULL; } if (sc->sc_io_res) { bus_release_resource(self, SYS_RES_MEMORY, 0, sc->sc_io_res); sc->sc_io_res = NULL; } usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc); return (0); }
static int dotg_obio_detach(device_t dev) { struct dotg_obio_softc *sc = device_get_softc(dev); device_t bdev; int err; if (sc->sc_dci.sc_bus.bdev) { bdev = sc->sc_dci.sc_bus.bdev; device_detach(bdev); device_delete_child(dev, bdev); } /* during module unload there are lots of children leftover */ device_delete_children(dev); if (sc->sc_dci.sc_irq_res && sc->sc_dci.sc_intr_hdl) { /* * only call dotg_obio_uninit() after dotg_obio_init() */ dotg_uninit(&sc->sc_dci); /* Stop OTG clock */ rt305x_sysctl_set(SYSCTL_CLKCFG1, rt305x_sysctl_get(SYSCTL_CLKCFG1) & ~SYSCTL_CLKCFG1_OTG_CLK_EN); err = bus_teardown_intr(dev, sc->sc_dci.sc_irq_res, sc->sc_dci.sc_intr_hdl); sc->sc_dci.sc_intr_hdl = NULL; } if (sc->sc_dci.sc_irq_res) { bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_dci.sc_irq_res); sc->sc_dci.sc_irq_res = NULL; } if (sc->sc_dci.sc_mem_res) { bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_dci.sc_mem_res); sc->sc_dci.sc_mem_res = NULL; } usb_bus_mem_free_all(&sc->sc_dci.sc_bus, NULL); return (0); }
static int ehci_obio_attach(device_t self) { ehci_softc_t *sc = device_get_softc(self); uint32_t reg; int err; int rid; /* setup controller interface softc */ reg = rt305x_sysctl_get(SYSCTL_SYSCFG1); reg |= SYSCTL_SYSCFG1_USB0_HOST_MODE; rt305x_sysctl_set(SYSCTL_SYSCFG1, reg); reg = rt305x_sysctl_get(SYSCTL_CLKCFG1); reg |= SYSCTL_CLKCFG1_UPHY0_CLK_EN; #ifdef MT7620 reg |= SYSCTL_CLKCFG1_UPHY1_CLK_EN; #endif rt305x_sysctl_set(SYSCTL_CLKCFG1, reg); reg = rt305x_sysctl_get(SYSCTL_RSTCTRL); reg |= SYSCTL_RSTCTRL_UPHY0 | SYSCTL_RSTCTRL_UPHY1; rt305x_sysctl_set(SYSCTL_RSTCTRL, reg); reg &= ~(SYSCTL_RSTCTRL_UPHY0 | SYSCTL_RSTCTRL_UPHY1); DELAY(100000); rt305x_sysctl_set(SYSCTL_RSTCTRL, reg); DELAY(100000); /* initialise some bus fields */ sc->sc_bus.parent = self; sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = EHCI_MAX_DEVICES; sc->sc_bus.dma_bits = 32; /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) { printf("No mem\n"); return (ENOMEM); } rid = 0; sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!sc->sc_io_res) { device_printf(self, "Could not map memory\n"); goto error; } sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = rman_get_size(sc->sc_io_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, RF_SHAREABLE | RF_ACTIVE); if (sc->sc_irq_res == NULL) { device_printf(self, "Could not allocate irq\n"); goto error; } sc->sc_bus.bdev = device_add_child(self, "usbus", -1); if (!(sc->sc_bus.bdev)) { device_printf(self, "Could not add USB device\n"); goto error; } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); device_set_desc(sc->sc_bus.bdev, EHCI_HC_DEVSTR); sprintf(sc->sc_vendor, "Ralink"); err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)ehci_interrupt, sc, &sc->sc_intr_hdl); if (err) { device_printf(self, "Could not setup irq, %d\n", err); sc->sc_intr_hdl = NULL; goto error; } err = ehci_init(sc); if (!err) { err = device_probe_and_attach(sc->sc_bus.bdev); } if (err) { device_printf(self, "USB init failed err=%d\n", err); goto error; } return (0); error: ehci_obio_detach(self); return (ENXIO); }
static void rt305x_sysctl_dump_config(device_t dev) { uint32_t val; #define DUMPREG(r) \ val = rt305x_sysctl_get(r); printf(" " #r "=%#08x\n", val) val = rt305x_sysctl_get(SYSCTL_CHIPID0_3); printf("\tChip ID: \"%c%c%c%c", (val >> 0 ) & 0xff, (val >> 8 ) & 0xff, (val >> 16) & 0xff, (val >> 24) & 0xff); val = rt305x_sysctl_get(SYSCTL_CHIPID4_7); printf("%c%c%c%c\"\n", (val >> 0 ) & 0xff, (val >> 8 ) & 0xff, (val >> 16) & 0xff, (val >> 24) & 0xff); DUMPREG(SYSCTL_SYSCFG); if ( val & SYSCTL_SYSCFG_INIC_EE_SDRAM) printf("\tGet SDRAM config from EEPROM\n"); if ( val & SYSCTL_SYSCFG_INIC_8MB_SDRAM) printf("\tBootstrap flag is set\n"); printf("\tGE0 mode %u\n", ((val & SYSCTL_SYSCFG_GE0_MODE_MASK) >> SYSCTL_SYSCFG_GE0_MODE_SHIFT)); if ( val & SYSCTL_SYSCFG_BOOT_ADDR_1F00) printf("\tBoot from 0x1f000000\n"); if ( val & SYSCTL_SYSCFG_BYPASS_PLL) printf("\tBypass PLL\n"); if ( val & SYSCTL_SYSCFG_BIG_ENDIAN) printf("\tBig Endian\n"); if ( val & SYSCTL_SYSCFG_CPU_CLK_SEL_384MHZ) printf("\tClock is 384MHz\n"); printf("\tBoot from %u\n", ((val & SYSCTL_SYSCFG_BOOT_FROM_MASK) >> SYSCTL_SYSCFG_BOOT_FROM_SHIFT)); printf("\tBootstrap test code %u\n", ((val & SYSCTL_SYSCFG_TEST_CODE_MASK) >> SYSCTL_SYSCFG_TEST_CODE_SHIFT)); printf("\tSRAM_CS mode %u\n", ((val & SYSCTL_SYSCFG_SRAM_CS_MODE_MASK) >> SYSCTL_SYSCFG_SRAM_CS_MODE_SHIFT)); printf("\t%umA SDRAM_CLK driving\n", (val & SYSCTL_SYSCFG_SDRAM_CLK_DRV)?12:8); DUMPREG(SYSCTL_CLKCFG0); printf("\tSDRAM_CLK_SKEW %uns\n", (val >> 30) & 0x03); DUMPREG(SYSCTL_CLKCFG1); if ( val & SYSCTL_CLKCFG1_PBUS_DIV_CLK_BY2) printf("\tPbus clock is 1/2 of System clock\n"); if ( val & SYSCTL_CLKCFG1_OTG_CLK_EN) printf("\tUSB OTG clock is enabled\n"); if ( val & SYSCTL_CLKCFG1_I2S_CLK_EN) printf("\tI2S clock is enabled\n"); printf("\tI2S clock is %s\n", (val & SYSCTL_CLKCFG1_I2S_CLK_SEL_EXT)? "external":"internal 15.625MHz"); printf("\tI2S clock divider %u\n", ((val & SYSCTL_CLKCFG1_I2S_CLK_DIV_MASK) >> SYSCTL_CLKCFG1_I2S_CLK_DIV_SHIFT)); if ( val & SYSCTL_CLKCFG1_PCM_CLK_EN) printf("\tPCM clock is enabled\n"); printf("\tPCM clock is %s\n", (val & SYSCTL_CLKCFG1_PCM_CLK_SEL_EXT)? "external":"internal 15.625MHz"); printf("\tPCM clock divider %u\n", ((val & SYSCTL_CLKCFG1_PCM_CLK_DIV_MASK) >> SYSCTL_CLKCFG1_PCM_CLK_DIV_SHIFT)); DUMPREG(SYSCTL_GPIOMODE); #undef DUMPREG return; }
static int dotg_obio_attach(device_t dev) { struct dwc_otg_softc *sc = device_get_softc(dev); uint32_t tmp; int err, rid; /* setup controller interface softc */ /* initialise some bus fields */ sc->sc_mode = DWC_MODE_HOST; sc->sc_bus.parent = dev; sc->sc_bus.devices = sc->sc_devices; sc->sc_bus.devices_max = DWC_OTG_MAX_DEVICES; sc->sc_bus.dma_bits = 32; /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_bus, USB_GET_DMA_TAG(dev), NULL)) { printf("No mem\n"); return (ENOMEM); } rid = 0; sc->sc_io_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE); if (!(sc->sc_io_res)) { printf("Can`t alloc MEM\n"); goto error; } sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); sc->sc_io_size = rman_get_size(sc->sc_io_res); rid = 0; sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, RF_ACTIVE); if (!(sc->sc_irq_res)) { printf("Can`t alloc IRQ\n"); goto error; } sc->sc_bus.bdev = device_add_child(dev, "usbus", -1); if (!(sc->sc_bus.bdev)) { printf("Can`t add usbus\n"); goto error; } device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); #if (__FreeBSD_version >= 700031) err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_TTY | INTR_MPSAFE, dwc_otg_filter_interrupt, dwc_otg_interrupt, sc, &sc->sc_intr_hdl); #else #error error err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,(driver_intr_t*)dwc_otg_interrupt, sc, &sc->sc_intr_hdl); #endif if (err) { sc->sc_intr_hdl = NULL; printf("Can`t set IRQ handle\n"); goto error; } /* Run clock for OTG core */ rt305x_sysctl_set(SYSCTL_CLKCFG1, rt305x_sysctl_get(SYSCTL_CLKCFG1) | SYSCTL_CLKCFG1_OTG_CLK_EN); tmp = rt305x_sysctl_get(SYSCTL_RSTCTRL); rt305x_sysctl_set(SYSCTL_RSTCTRL, tmp | SYSCTL_RSTCTRL_OTG); DELAY(100); /* * Docs say that RSTCTRL bits for RT305x are W1C, so there should * be no need for the below, but who really knows? */ // rt305x_sysctl_set(SYSCTL_RSTCTRL, tmp & ~SYSCTL_RSTCTRL_OTG); // DELAY(100); err = dwc_otg_init(sc); if (err) printf("dotg_init fail\n"); if (!err) { err = device_probe_and_attach(sc->sc_bus.bdev); if (err) printf("device_probe_and_attach fail %d\n", err); } if (err) { goto error; } return (0); error: dotg_obio_detach(dev); return (ENXIO); }
static int dotg_obio_attach(device_t dev) { struct dotg_obio_softc *sc = device_get_softc(dev); int err; /* setup controller interface softc */ /* initialise some bus fields */ sc->sc_dci.sc_dev = dev; sc->sc_dci.sc_bus.parent = dev; sc->sc_dci.sc_bus.devices = sc->sc_dci.sc_devices; sc->sc_dci.sc_bus.devices_max = DOTG_MAX_DEVICES; /* get all DMA memory */ if (usb_bus_mem_alloc_all(&sc->sc_dci.sc_bus, USB_GET_DMA_TAG(dev), NULL)) { printf("No mem\n"); return (ENOMEM); } sc->sc_dci.sc_mem_rid = 0; sc->sc_dci.sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_dci.sc_irq_rid, RF_ACTIVE); if (!(sc->sc_dci.sc_mem_res)) { printf("Can`t alloc MEM\n"); goto error; } sc->sc_dci.sc_bst = rman_get_bustag(sc->sc_dci.sc_mem_res); sc->sc_dci.sc_bsh = rman_get_bushandle(sc->sc_dci.sc_mem_res); sc->sc_dci.sc_irq_rid = 0; sc->sc_dci.sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->sc_dci.sc_irq_rid, RF_SHAREABLE| RF_ACTIVE); if (!(sc->sc_dci.sc_irq_res)) { printf("Can`t alloc IRQ\n"); goto error; } sc->sc_dci.sc_bus.bdev = device_add_child(dev, "usbus", -1); if (!(sc->sc_dci.sc_bus.bdev)) { printf("Can`t add usbus\n"); goto error; } device_set_ivars(sc->sc_dci.sc_bus.bdev, &sc->sc_dci.sc_bus); #if (__FreeBSD_version >= 700031) err = bus_setup_intr(dev, sc->sc_dci.sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, NULL, (driver_intr_t *)dotg_interrupt, sc, &sc->sc_dci.sc_intr_hdl); #else err = bus_setup_intr(dev, sc->sc_dci.sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, (driver_intr_t *)dotg_interrupt, sc, &sc->sc_dci.sc_intr_hdl); #endif if (err) { sc->sc_dci.sc_intr_hdl = NULL; printf("Can`t set IRQ handle\n"); goto error; } /* Run clock for OTG core */ rt305x_sysctl_set(SYSCTL_CLKCFG1, rt305x_sysctl_get(SYSCTL_CLKCFG1) | SYSCTL_CLKCFG1_OTG_CLK_EN); rt305x_sysctl_set(SYSCTL_RSTCTRL, SYSCTL_RSTCTRL_OTG); DELAY(100); err = dotg_init(&sc->sc_dci); if (err) printf("dotg_init fail\n"); if (!err) { err = device_probe_and_attach(sc->sc_dci.sc_bus.bdev); if (err) printf("device_probe_and_attach fail\n"); } if (err) { goto error; } return (0); error: dotg_obio_detach(dev); return (ENXIO); }