int c2h_evt_read23a(struct rtw_adapter *adapter, u8 *buf) { int ret = _FAIL; struct c2h_evt_hdr *c2h_evt; int i; u8 trigger; if (buf == NULL) goto exit; trigger = rtl8723au_read8(adapter, REG_C2HEVT_CLEAR); if (trigger == C2H_EVT_HOST_CLOSE) goto exit; /* Not ready */ else if (trigger != C2H_EVT_FW_CLOSE) goto clear_evt; /* Not a valid value */ c2h_evt = (struct c2h_evt_hdr *)buf; memset(c2h_evt, 0, 16); *buf = rtl8723au_read8(adapter, REG_C2HEVT_MSG_NORMAL); *(buf + 1) = rtl8723au_read8(adapter, REG_C2HEVT_MSG_NORMAL + 1); RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read23a(): ", &c2h_evt, sizeof(c2h_evt)); if (0) { DBG_8723A("%s id:%u, len:%u, seq:%u, trigger:0x%02x\n", __func__, c2h_evt->id, c2h_evt->plen, c2h_evt->seq, trigger); } /* Read the content */ for (i = 0; i < c2h_evt->plen; i++) c2h_evt->payload[i] = rtl8723au_read8(adapter, REG_C2HEVT_MSG_NORMAL + sizeof(*c2h_evt) + i); RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read23a(): Command Content:\n", c2h_evt->payload, c2h_evt->plen); ret = _SUCCESS; clear_evt: /* * Clear event to notify FW we have read the command. * If this field isn't clear, the FW won't update the * next command message. */ c2h_evt_clear23a(adapter); exit: return ret; }
void rtl8723a_bcn_valid(struct rtw_adapter *padapter) { /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */ rtl8723au_write8(padapter, REG_TDECTRL + 2, rtl8723au_read8(padapter, REG_TDECTRL + 2) | BIT(0)); }
void rtl8723a_set_ampdu_min_space(struct rtw_adapter *padapter, u8 MinSpacingToSet) { u8 SecMinSpace; if (MinSpacingToSet <= 7) { switch (padapter->securitypriv.dot11PrivacyAlgrthm) { case 0: case WLAN_CIPHER_SUITE_CCMP: SecMinSpace = 0; break; case WLAN_CIPHER_SUITE_WEP40: case WLAN_CIPHER_SUITE_WEP104: case WLAN_CIPHER_SUITE_TKIP: SecMinSpace = 6; break; default: SecMinSpace = 7; break; } if (MinSpacingToSet < SecMinSpace) MinSpacingToSet = SecMinSpace; MinSpacingToSet |= rtl8723au_read8(padapter, REG_AMPDU_MIN_SPACE) & 0xf8; rtl8723au_write8(padapter, REG_AMPDU_MIN_SPACE, MinSpacingToSet); } }
/* Turn off LED according to LedPin specified. */ void SwLedOff23a(struct rtw_adapter *padapter, struct led_8723a *pLed) { u8 LedCfg = 0; /* struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); */ if ((padapter->bSurpriseRemoved) || (padapter->bDriverStopped)) goto exit; switch (pLed->LedPin) { case LED_PIN_GPIO0: break; case LED_PIN_LED0: /* SW control led0 on. */ rtl8723au_write8(padapter, REG_LEDCFG0, (LedCfg&0xf0)|BIT(5)|BIT(6)); break; case LED_PIN_LED1: /* SW control led1 on. */ rtl8723au_write8(padapter, REG_LEDCFG1, (LedCfg&0x00)|BIT(5)|BIT(6)); break; case LED_PIN_LED2: LedCfg = rtl8723au_read8(padapter, REG_LEDCFG2); /* SW control led1 on. */ rtl8723au_write8(padapter, REG_LEDCFG2, (LedCfg&0x80)|BIT(3)|BIT(5)); break; default: break; } exit: pLed->bLedOn = false; }
/* Turn on LED according to LedPin specified. */ void SwLedOn23a(struct rtw_adapter *padapter, struct led_8723a *pLed) { u8 LedCfg = 0; if ((padapter->bSurpriseRemoved == true) || (padapter->bDriverStopped == true)) return; switch (pLed->LedPin) { case LED_PIN_GPIO0: break; case LED_PIN_LED0: /* SW control led0 on. */ rtl8723au_write8(padapter, REG_LEDCFG0, (LedCfg&0xf0)|BIT(5)|BIT(6)); break; case LED_PIN_LED1: /* SW control led1 on. */ rtl8723au_write8(padapter, REG_LEDCFG1, (LedCfg&0x00)|BIT(6)); break; case LED_PIN_LED2: LedCfg = rtl8723au_read8(padapter, REG_LEDCFG2); /* SW control led1 on. */ rtl8723au_write8(padapter, REG_LEDCFG2, (LedCfg&0x80)|BIT(5)); break; default: break; } pLed->bLedOn = true; }
bool rtl8723a_get_bcn_valid(struct rtw_adapter *padapter) { bool retval; retval = (rtl8723au_read8(padapter, REG_TDECTRL + 2) & BIT(0)) ? true : false; return retval; }
void rtl8723a_set_media_status1(struct rtw_adapter *padapter, u8 status) { u8 val8; val8 = rtl8723au_read8(padapter, MSR) & 0x03; val8 |= status << 2; rtl8723au_write8(padapter, MSR, val8); }
static u8 _is_fw_read_cmd_down(struct rtw_adapter *padapter, u8 msgbox_num) { u8 read_down = false; int retry_cnts = 100; u8 valid; do { valid = rtl8723au_read8(padapter, REG_HMETFR) & BIT(msgbox_num); if (0 == valid) read_down = true; } while ((!read_down) && (retry_cnts--)); return read_down; }
void rtl8723a_fifo_cleanup(struct rtw_adapter *padapter) { #define RW_RELEASE_EN BIT(18) #define RXDMA_IDLE BIT(17) struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; u8 trycnt = 100; /* pause tx */ rtl8723au_write8(padapter, REG_TXPAUSE, 0xff); /* keep sn */ padapter->xmitpriv.nqos_ssn = rtl8723au_read8(padapter, REG_NQOS_SEQ); if (pwrpriv->bkeepfwalive != true) { u32 v32; /* RX DMA stop */ v32 = rtl8723au_read32(padapter, REG_RXPKT_NUM); v32 |= RW_RELEASE_EN; rtl8723au_write32(padapter, REG_RXPKT_NUM, v32); do { v32 = rtl8723au_read32(padapter, REG_RXPKT_NUM) & RXDMA_IDLE; if (!v32) break; } while (trycnt--); if (trycnt == 0) DBG_8723A("Stop RX DMA failed......\n"); /* RQPN Load 0 */ rtl8723au_write16(padapter, REG_RQPN_NPQ, 0); rtl8723au_write32(padapter, REG_RQPN, 0x80000000); mdelay(10); } }
void HalSetBrateCfg23a(struct rtw_adapter *padapter, u8 *mBratesOS) { struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); u8 i, is_brate, brate; u16 brate_cfg = 0; u8 rate_index; for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK; brate = mBratesOS[i] & 0x7f; if (is_brate) { switch (brate) { case IEEE80211_CCK_RATE_1MB: brate_cfg |= RATE_1M; break; case IEEE80211_CCK_RATE_2MB: brate_cfg |= RATE_2M; break; case IEEE80211_CCK_RATE_5MB: brate_cfg |= RATE_5_5M; break; case IEEE80211_CCK_RATE_11MB: brate_cfg |= RATE_11M; break; case IEEE80211_OFDM_RATE_6MB: brate_cfg |= RATE_6M; break; case IEEE80211_OFDM_RATE_9MB: brate_cfg |= RATE_9M; break; case IEEE80211_OFDM_RATE_12MB: brate_cfg |= RATE_12M; break; case IEEE80211_OFDM_RATE_18MB: brate_cfg |= RATE_18M; break; case IEEE80211_OFDM_RATE_24MB: brate_cfg |= RATE_24M; break; case IEEE80211_OFDM_RATE_36MB: brate_cfg |= RATE_36M; break; case IEEE80211_OFDM_RATE_48MB: brate_cfg |= RATE_48M; break; case IEEE80211_OFDM_RATE_54MB: brate_cfg |= RATE_54M; break; } } } /* 2007.01.16, by Emily */ /* Select RRSR (in Legacy-OFDM and CCK) */ /* For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. */ /* We do not use other rates. */ /* 2011.03.30 add by Luke Lee */ /* CCK 2M ACK should be disabled for some BCM and Atheros AP IOT */ /* because CCK 2M has poor TXEVM */ /* CCK 5.5M & 11M ACK should be enabled for better performance */ brate_cfg = (brate_cfg | 0xd) & 0x15d; pHalData->BasicRateSet = brate_cfg; brate_cfg |= 0x01; /* default enable 1M ACK rate */ DBG_8723A("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", brate_cfg); /* Set RRSR rate table. */ rtl8723au_write8(padapter, REG_RRSR, brate_cfg & 0xff); rtl8723au_write8(padapter, REG_RRSR + 1, (brate_cfg >> 8) & 0xff); rtl8723au_write8(padapter, REG_RRSR + 2, rtl8723au_read8(padapter, REG_RRSR + 2) & 0xf0); rate_index = 0; /* Set RTS initial rate */ while (brate_cfg > 0x1) { brate_cfg >>= 1; rate_index++; } /* Ziv - Check */ rtl8723au_write8(padapter, REG_INIRTS_RATE_SEL, rate_index); }
void rtl8723a_set_FwJoinBssReport_cmd(struct rtw_adapter *padapter, u8 mstatus) { struct joinbssrpt_parm JoinBssRptParm; struct hal_data_8723a *pHalData = GET_HAL_DATA(padapter); struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; DBG_8723A("%s mstatus(%x)\n", __func__, mstatus); if (mstatus == 1) { bool bRecover = false; u8 v8; /* We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. */ /* Suggested by filen. Added by tynli. */ rtl8723au_write16(padapter, REG_BCN_PSR_RPT, 0xC000|pmlmeinfo->aid); /* Do not set TSF again here or vWiFi beacon DMA INT will not work. */ /* correct_TSF23a(padapter, pmlmeext); */ /* Hw sequende enable by dedault. 2010.06.23. by tynli. */ /* rtl8723au_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF)); */ /* rtl8723au_write8(padapter, REG_HWSEQ_CTRL, 0xFF); */ /* set REG_CR bit 8 */ v8 = rtl8723au_read8(padapter, REG_CR+1); v8 |= BIT(0); /* ENSWBCN */ rtl8723au_write8(padapter, REG_CR+1, v8); /* Disable Hw protection for a time which revserd for Hw sending beacon. */ /* Fix download reserved page packet fail that access collision with the protection time. */ /* 2010.05.11. Added by tynli. */ /* SetBcnCtrlReg23a(padapter, 0, BIT(3)); */ /* SetBcnCtrlReg23a(padapter, BIT(4), 0); */ SetBcnCtrlReg23a(padapter, BIT(4), BIT(3)); /* Set FWHW_TXQ_CTRL 0x422[6]= 0 to tell Hw the packet is not a real beacon frame. */ if (pHalData->RegFwHwTxQCtrl & BIT(6)) bRecover = true; /* To tell Hw the packet is not a real beacon frame. */ /* U1bTmp = rtl8723au_read8(padapter, REG_FWHW_TXQ_CTRL+2); */ rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl & ~BIT(6)); pHalData->RegFwHwTxQCtrl &= ~BIT(6); SetFwRsvdPagePkt(padapter, 0); /* 2010.05.11. Added by tynli. */ SetBcnCtrlReg23a(padapter, BIT(3), BIT(4)); /* To make sure that if there exists an adapter which would like to send beacon. */ /* If exists, the origianl value of 0x422[6] will be 1, we should check this to */ /* prevent from setting 0x422[6] to 0 after download reserved page, or it will cause */ /* the beacon cannot be sent by HW. */ /* 2010.06.23. Added by tynli. */ if (bRecover) { rtl8723au_write8(padapter, REG_FWHW_TXQ_CTRL + 2, pHalData->RegFwHwTxQCtrl | BIT(6)); pHalData->RegFwHwTxQCtrl |= BIT(6); } /* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */ v8 = rtl8723au_read8(padapter, REG_CR+1); v8 &= ~BIT(0); /* ~ENSWBCN */ rtl8723au_write8(padapter, REG_CR+1, v8); } JoinBssRptParm.OpMode = mstatus; FillH2CCmd(padapter, JOINBSS_RPT_EID, sizeof(JoinBssRptParm), (u8 *)&JoinBssRptParm); }
u8 HalPwrSeqCmdParsing23a(struct rtw_adapter *padapter, u8 CutVersion, u8 FabVersion, u8 InterfaceType, struct wlan_pwr_cfg PwrSeqCmd[]) { struct wlan_pwr_cfg PwrCfgCmd = { 0 }; u8 bPollingBit = false; u32 AryIdx = 0; u8 value = 0; u32 offset = 0; u32 pollingCount = 0; /* polling autoload done. */ u32 maxPollingCnt = 5000; do { PwrCfgCmd = PwrSeqCmd[AryIdx]; RT_TRACE(_module_hal_init_c_, _drv_info_, ("HalPwrSeqCmdParsing23a: offset(%#x) cut_msk(%#x) " "fab_msk(%#x) interface_msk(%#x) base(%#x) cmd(%#x) " "msk(%#x) value(%#x)\n", GET_PWR_CFG_OFFSET(PwrCfgCmd), GET_PWR_CFG_CUT_MASK(PwrCfgCmd), GET_PWR_CFG_FAB_MASK(PwrCfgCmd), GET_PWR_CFG_INTF_MASK(PwrCfgCmd), GET_PWR_CFG_BASE(PwrCfgCmd), GET_PWR_CFG_CMD(PwrCfgCmd), GET_PWR_CFG_MASK(PwrCfgCmd), GET_PWR_CFG_VALUE(PwrCfgCmd))); /* 2 Only Handle the command whose FAB, CUT, and Interface are matched */ if ((GET_PWR_CFG_FAB_MASK(PwrCfgCmd) & FabVersion) && (GET_PWR_CFG_CUT_MASK(PwrCfgCmd) & CutVersion) && (GET_PWR_CFG_INTF_MASK(PwrCfgCmd) & InterfaceType)) { switch (GET_PWR_CFG_CMD(PwrCfgCmd)) { case PWR_CMD_READ: RT_TRACE(_module_hal_init_c_, _drv_info_, ("HalPwrSeqCmdParsing23a: " "PWR_CMD_READ\n")); break; case PWR_CMD_WRITE: RT_TRACE(_module_hal_init_c_, _drv_info_, ("HalPwrSeqCmdParsing23a: " "PWR_CMD_WRITE\n")); offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); /* Read the value from system register */ value = rtl8723au_read8(padapter, offset); value &= ~(GET_PWR_CFG_MASK(PwrCfgCmd)); value |= (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd)); /* Write the value back to sytem register */ rtl8723au_write8(padapter, offset, value); break; case PWR_CMD_POLLING: RT_TRACE(_module_hal_init_c_, _drv_info_, ("HalPwrSeqCmdParsing23a: " "PWR_CMD_POLLING\n")); bPollingBit = false; offset = GET_PWR_CFG_OFFSET(PwrCfgCmd); do { value = rtl8723au_read8(padapter, offset); value &= GET_PWR_CFG_MASK(PwrCfgCmd); if (value == (GET_PWR_CFG_VALUE(PwrCfgCmd) & GET_PWR_CFG_MASK(PwrCfgCmd))) bPollingBit = true; else udelay(10); if (pollingCount++ > maxPollingCnt) { DBG_8723A("Fail to polling " "Offset[%#x]\n", offset); return false; } } while (!bPollingBit); break; case PWR_CMD_DELAY: RT_TRACE(_module_hal_init_c_, _drv_info_, ("HalPwrSeqCmdParsing23a: " "PWR_CMD_DELAY\n")); if (GET_PWR_CFG_VALUE(PwrCfgCmd) == PWRSEQ_DELAY_US) udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd)); else udelay(GET_PWR_CFG_OFFSET(PwrCfgCmd) * 1000); break; case PWR_CMD_END: /* When this command is parsed, end the process */ RT_TRACE(_module_hal_init_c_, _drv_info_, ("HalPwrSeqCmdParsing23a: " "PWR_CMD_END\n")); return true; break; default: RT_TRACE(_module_hal_init_c_, _drv_err_, ("HalPwrSeqCmdParsing23a: " "Unknown CMD!!\n")); break; } } AryIdx++; /* Add Array Index */ } while (1); return true; }