static void _rtl92s_dm_dynamic_txpower( struct ieee80211_hw *hw ) { struct rtl_priv *rtlpriv = rtl_priv( hw ); struct rtl_phy *rtlphy = &( rtlpriv->phy ); struct rtl_mac *mac = rtl_mac( rtl_priv( hw ) ); long undec_sm_pwdb; long txpwr_threshold_lv1, txpwr_threshold_lv2; /* 2T2R TP issue */ if ( rtlphy->rf_type == RF_2T2R ) return; if ( !rtlpriv->dm.dynamic_txpower_enable || rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE ) { rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL; return; } if ( ( mac->link_state < MAC80211_LINKED ) && ( rtlpriv->dm.entry_min_undec_sm_pwdb == 0 ) ) { RT_TRACE( rtlpriv, COMP_POWER, DBG_TRACE, "Not connected to any\n" ); rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL; rtlpriv->dm.last_dtp_lvl = TX_HIGHPWR_LEVEL_NORMAL; return; } if ( mac->link_state >= MAC80211_LINKED ) { if ( mac->opmode == NL80211_IFTYPE_ADHOC ) { undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb; RT_TRACE( rtlpriv, COMP_POWER, DBG_LOUD, "AP Client PWDB = 0x%lx\n", undec_sm_pwdb ); } else { undec_sm_pwdb = rtlpriv->dm.undec_sm_pwdb; RT_TRACE( rtlpriv, COMP_POWER, DBG_LOUD, "STA Default Port PWDB = 0x%lx\n", undec_sm_pwdb ); } } else { undec_sm_pwdb = rtlpriv->dm.entry_min_undec_sm_pwdb; RT_TRACE( rtlpriv, COMP_POWER, DBG_LOUD, "AP Ext Port PWDB = 0x%lx\n", undec_sm_pwdb ); } txpwr_threshold_lv2 = TX_POWER_NEAR_FIELD_THRESH_LVL2; txpwr_threshold_lv1 = TX_POWER_NEAR_FIELD_THRESH_LVL1; if ( rtl_get_bbreg( hw, 0xc90, MASKBYTE0 ) == 1 ) rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL; else if ( undec_sm_pwdb >= txpwr_threshold_lv2 ) rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL2; else if ( ( undec_sm_pwdb < ( txpwr_threshold_lv2 - 3 ) ) && ( undec_sm_pwdb >= txpwr_threshold_lv1 ) ) rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL1; else if ( undec_sm_pwdb < ( txpwr_threshold_lv1 - 3 ) ) rtlpriv->dm.dynamic_txhighpower_lvl = TX_HIGHPWR_LEVEL_NORMAL; if ( ( rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl ) ) rtl92s_phy_set_txpower( hw, rtlphy->current_channel ); rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl; }
int rtl92su_hw_init(struct ieee80211_hw *hw) { struct rtl_priv *rtlpriv = rtl_priv(hw); struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); struct rtl_phy *rtlphy = &(rtlpriv->phy); struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw)); int err = 0; bool rtstatus = true; u8 i; int wdcapra_add[] = { REG_EDCA_BE_PARAM, REG_EDCA_BK_PARAM, REG_EDCA_VI_PARAM, REG_EDCA_VO_PARAM}; u8 secr_value = 0x0; /* 1. MAC Initialize */ /* Before FW download, we have to set some MAC register */ err = _rtl92su_macconfig_before_fwdownload(hw); if (err) { RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "Failed to get the device ready for the firmware (%d)\n", err); return err; } rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv, REG_PMC_FSM) >> 16) & 0xF); /* 2. download firmware */ rtstatus = rtl92s_download_fw(hw); if (!rtstatus) { RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "Failed to download FW. Init HW without FW now... Please copy FW into /lib/firmware/rtlwifi\n"); return -ENOENT; } /* After FW download, we have to reset MAC register */ _rtl92su_macconfig_after_fwdownload(hw); /*Retrieve default FW Cmd IO map. */ rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, REG_LBUS_MON_ADDR); rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, REG_LBUS_ADDR_MASK); /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */ rtstatus = rtl92s_phy_mac_config(hw); if (!rtstatus) { RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n"); return -EINVAL; } /* because last function modify RCR, so we update * rcr var here, or TP will unstable for receive_config * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252 */ /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */ /* We must set flag avoid BB/RF config period later!! */ rtl_write_word(rtlpriv, CMDR, 0x37FC); /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */ rtstatus = rtl92s_phy_bb_config(hw); if (!rtstatus) { RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n"); return -ENODEV; } /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */ /* Before initalizing RF. We can not use FW to do RF-R/W. */ rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; /* Before RF-R/W we must execute the IO from Scott's suggestion. */ rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0xDB); if (rtlhal->version == VERSION_8192S_ACUT) rtl_write_byte(rtlpriv, REG_SPS1_CTRL + 3, 0x07); else rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07); rtstatus = rtl92s_phy_rf_config(hw); if (!rtstatus) { RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n"); return -EOPNOTSUPP; } /* After read predefined TXT, we must set BB/MAC/RF * register as our requirement */ rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw, (enum radio_path)0, RF_CHNLBW, RFREG_OFFSET_MASK); rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw, (enum radio_path)1, RF_CHNLBW, RFREG_OFFSET_MASK); /*---- Set CCK and OFDM Block "ON"----*/ rtl_set_bbreg(hw, REG_RFPGA0_RFMOD, BCCKEN, 0x1); rtl_set_bbreg(hw, REG_RFPGA0_RFMOD, BOFDMEN, 0x1); /*3 Set Hardware(Do nothing now) */ _rtl92su_hw_configure(hw); /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */ /* TX power index for different rate set. */ /* Get original hw reg values */ rtl92s_phy_get_hw_reg_originalvalue(hw); /* Write correct tx power index */ rtl92s_phy_set_txpower(hw, rtlphy->current_channel); /* We must set MAC address after firmware download. */ for (i = 0; i < 6; i++) rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]); /* We enable high power and RA related mechanism after NIC * initialized. */ if (hal_get_firmwareversion(rtlpriv) >= 0x35) { /* Fw v.53 and later. */ rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT); } else if (hal_get_firmwareversion(rtlpriv) == 0x34) { /* Fw v.52. */ rtl_write_dword(rtlpriv, REG_WFM5, FW_RA_INIT); rtl92s_phy_chk_fwcmd_iodone(hw); } else { /* Compatible earlier FW version. */ rtl_write_dword(rtlpriv, REG_WFM5, FW_RA_RESET); rtl92s_phy_chk_fwcmd_iodone(hw); rtl_write_dword(rtlpriv, REG_WFM5, FW_RA_ACTIVE); rtl92s_phy_chk_fwcmd_iodone(hw); rtl_write_dword(rtlpriv, REG_WFM5, FW_RA_REFRESH); rtl92s_phy_chk_fwcmd_iodone(hw); } /* Security related * 1. Clear all H/W keys. * 2. Enable H/W encryption/decryption. */ rtl_cam_reset_all_entry(hw); secr_value |= SCR_TXENCENABLE; secr_value |= SCR_RXENCENABLE; secr_value |= SCR_NOSKMC; rtl_write_byte(rtlpriv, REG_SECR, secr_value); for (i = 0; i < 4; i++) rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322); if (rtlphy->rf_type == RF_1T2R) { bool mrc2set = true; /* Turn on B-Path */ rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set); } rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON); rtl92s_dm_init(hw); return err; }