u4Byte mptbt_switch_RF(PADAPTER Adapter, u1Byte Enter)
{
u2Byte tmp_2byte = 0;
//Enter test mode
if (Enter) {
////1>. close WiFi RF
mptbt_close_WiFiRF(Adapter);
////2>. change ant switch to BT
tmp_2byte = rtw_read16(Adapter, 0x860);
tmp_2byte = tmp_2byte | BIT(9);
tmp_2byte = tmp_2byte & (~BIT(8));
rtw_write16(Adapter, 0x860, tmp_2byte);
rtw_write16(Adapter, 0x870, 0x300);
} else {
////1>. Open WiFi RF
mptbt_open_WiFiRF(Adapter);
////2>. change ant switch back
tmp_2byte = rtw_read16(Adapter, 0x860);
tmp_2byte = tmp_2byte | BIT(8);
tmp_2byte = tmp_2byte & (~BIT(9));
rtw_write16(Adapter, 0x860, tmp_2byte);
rtw_write16(Adapter, 0x870, 0x300);
}
return 0;
}
BOOLEAN
rtl8192d_PHY_EnableAnotherPHY(
IN PADAPTER Adapter,
IN BOOLEAN bMac0
)
{
u8 u1bTmp;
#ifdef CONFIG_PCI_HCI
u8 Direct = bMac0==_TRUE?BIT3|BIT2:BIT3;
#endif //CONFIG_PCI_HCI
u8 MAC_REG = bMac0==_TRUE?REG_MAC1:REG_MAC0;
u8 MAC_ON_BIT = bMac0==_TRUE?MAC1_ON:MAC0_ON;
BOOLEAN bResult = _TRUE; //true: need to enable BB/RF power
#ifdef CONFIG_USB_HCI
u32 MaskForPHYSet = 0;
#endif
//RT_TRACE(COMP_RF, DBG_LOUD, ("===>PHY_EnableAnotherPHY\n"));
//MAC0 Need PHY1 load radio_b.txt . Driver use DBI to write.
u1bTmp = rtw_read8(Adapter, MAC_REG);
if (!(u1bTmp&MAC_ON_BIT))
{
//RT_TRACE(COMP_INIT, DBG_LOUD, ("PHY_EnableAnotherPHY enable BB & RF\n"));
// Enable BB and RF power
#ifdef CONFIG_PCI_HCI
MpWritePCIDwordDBI8192D(Adapter,
REG_SYS_ISO_CTRL,
MpReadPCIDwordDBI8192D(Adapter, REG_SYS_ISO_CTRL, Direct)|BIT29|BIT16|BIT17,
Direct);
#elif defined(CONFIG_USB_HCI)
if(bMac0)
MaskForPHYSet = MAC0_ACCESS_PHY1;
else
MaskForPHYSet = MAC1_ACCESS_PHY0;
rtw_write16(Adapter, REG_SYS_FUNC_EN|MaskForPHYSet, rtw_read16(Adapter, REG_SYS_FUNC_EN|MaskForPHYSet)&0xFFFC);
rtw_write16(Adapter, REG_SYS_FUNC_EN|MaskForPHYSet, rtw_read16(Adapter, REG_SYS_FUNC_EN|MaskForPHYSet)|BIT13|BIT0|BIT1);
#endif
}
else
{
// We think if MAC1 is ON,then radio_a.txt and radio_b.txt has been load.
bResult = _FALSE;
}
//RT_TRACE(COMP_RF, DBG_LOUD, ("<===PHY_EnableAnotherPHY\n"));
return bResult;
}
static void _restore_network_status(_adapter *padapter)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network));
unsigned short caps;
u8 join_type;
#if 1
//=======================================================
// reset related register of Beacon control
//set MSR to nolink
Set_MSR(padapter, _HW_STATE_NOLINK_);
// reject all data frame
rtw_write16(padapter, REG_RXFLTMAP2,0x00);
//reset TSF
rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
// disable update TSF
SetBcnCtrlReg(padapter, BIT(4), 0);
//=======================================================
rtw_joinbss_reset(padapter);
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
//pmlmeinfo->assoc_AP_vendor = maxAP;
if (padapter->registrypriv.wifi_spec) {
// for WiFi test, follow WMM test plan spec
rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002F431C);
rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005E541C);
rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x0000A525);
rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A549);
// for WiFi test, mixed mode with intel STA under bg mode throughput issue
if (padapter->mlmepriv.htpriv.ht_option == 0)
rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x00004320);
} else {
rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002F3217);
rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005E4317);
rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x00105320);
rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A444);
}
//disable dynamic functions, such as high power, DIG
//Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
#endif
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
join_type = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
Set_MSR(padapter, (pmlmeinfo->state & 0x3));
mlmeext_joinbss_event_callback(padapter, 1);
//restore Sequence No.
rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn);
}
static u8 _InitPowerOn(PADAPTER padapter)
{
u8 status = _SUCCESS;
u16 value16=0;
u8 value8 = 0;
// RSV_CTRL 0x1C[7:0] = 0x00 // unlock ISO/CLK/Power control register
rtw_write8(padapter, REG_RSV_CTRL, 0x0);
// HW Power on sequence
if(!HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, rtl8723A_card_enable_flow ))
return _FAIL;
// 0x04[19] = 1, suggest by Jackie 2011.05.09, reset 8051
value8 = rtw_read8(padapter, REG_APS_FSMCO+2);
rtw_write8(padapter,REG_APS_FSMCO+2,(value8|BIT3));
// Enable MAC DMA/WMAC/SCHEDULE/SEC block
// Set CR bit10 to enable 32k calibration. Suggested by SD1 Gimmy. Added by tynli. 2011.08.31.
value16 = rtw_read16(padapter, REG_CR);
value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN
| PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC | CALTMR_EN);
rtw_write16(padapter, REG_CR, value16);
//for Efuse PG, suggest by Jackie 2011.11.23
PHY_SetBBReg(padapter, REG_EFUSE_CTRL, BIT28|BIT29|BIT30, 0x06);
return status;
}
s32 MPT_InitializeAdapter(struct adapter *pAdapter, u8 Channel)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(pAdapter);
s32 rtStatus = _SUCCESS;
struct mpt_context *pMptCtx = &pAdapter->mppriv.MptCtx;
struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv;
/* HW Initialization for 8190 MPT. */
/* SW Initialization for 8190 MP. */
pMptCtx->bMptDrvUnload = false;
pMptCtx->bMassProdTest = false;
pMptCtx->bMptIndexEven = true; /* default gain index is -6.0db */
pMptCtx->h2cReqNum = 0x0;
/* Init mpt event. */
/* init for BT MP */
pMptCtx->bMptWorkItemInProgress = false;
pMptCtx->CurrMptAct = NULL;
/* */
/* Don't accept any packets */
rtw_write32(pAdapter, REG_RCR, 0);
PHY_IQCalibrate(pAdapter, false);
dm_CheckTXPowerTracking(&pHalData->odmpriv); /* trigger thermal meter */
PHY_LCCalibrate(pAdapter);
pMptCtx->backup0xc50 = (u8)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
pMptCtx->backup0xc58 = (u8)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
pMptCtx->backup0xc30 = (u8)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
pMptCtx->backup0x52_RF_A = (u8)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
pMptCtx->backup0x52_RF_B = (u8)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
/* set ant to wifi side in mp mode */
rtw_write16(pAdapter, 0x870, 0x300);
rtw_write16(pAdapter, 0x860, 0x110);
if (pAdapter->registrypriv.mp_mode == 1)
pmlmepriv->fw_state = WIFI_MP_STATE;
return rtStatus;
}
static void _restore_network_status(struct adapter *padapter)
{
struct hal_data_8188e *pHalData = GET_HAL_DATA(padapter);
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
struct wlan_bssid_ex *pnetwork = (struct wlan_bssid_ex*)(&(pmlmeinfo->network));
unsigned short caps;
u8 join_type;
/* */
/* reset related register of Beacon control */
/* set MSR to nolink */
Set_MSR(padapter, _HW_STATE_NOLINK_);
/* reject all data frame */
rtw_write16(padapter, REG_RXFLTMAP2,0x00);
/* reset TSF */
rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
/* disable update TSF */
SetBcnCtrlReg(padapter, BIT(4), 0);
/* */
rtw_joinbss_reset(padapter);
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
if (padapter->registrypriv.wifi_spec) {
/* for WiFi test, follow WMM test plan spec */
rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002F431C);
rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005E541C);
rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x0000A525);
rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A549);
/* for WiFi test, mixed mode with intel STA under bg mode throughput issue */
if (padapter->mlmepriv.htpriv.ht_option == 0)
rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x00004320);
} else {
rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002F3217);
rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005E4317);
rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x00105320);
rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A444);
}
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
join_type = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
Set_MSR(padapter, (pmlmeinfo->state & 0x3));
mlmeext_joinbss_event_callback(padapter, 1);
/* restore Sequence No. */
rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn);
}
static VOID
_InitPageBoundary(
IN PADAPTER Adapter
)
{
// RX Page Boundary
//srand(static_cast<unsigned int>(time(NULL)) );
u16 rxff_bndy = 0x27FF;//(rand() % 1) ? 0x27FF : 0x23FF;
rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
// TODO: ?? shall we set tx boundary?
}
void write_macreg(struct adapter *padapter, u32 addr, u32 val, u32 sz)
{
switch (sz) {
case 1:
rtw_write8(padapter, addr, (u8)val);
break;
case 2:
rtw_write16(padapter, addr, (u16)val);
break;
case 4:
rtw_write32(padapter, addr, val);
break;
default:
break;
}
}
int proc_set_write_reg(struct file* f, const char *buffer,
unsigned long count, void *data)
{
struct net_device *dev = (struct net_device *)data;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
u32 addr, val, len;
if (count < 3)
{
DBG_871X("argument size is less than 3\n");
return -EFAULT;
}
if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) {
int num = sscanf(tmp, "%x %x %x", &addr, &val, &len);
if (num != 3) {
DBG_871X("invalid write_reg parameter!\n");
return count;
}
switch(len)
{
case 1:
rtw_write8(padapter, addr, (u8)val);
break;
case 2:
rtw_write16(padapter, addr, (u16)val);
break;
case 4:
rtw_write32(padapter, addr, val);
break;
default:
DBG_871X("error write length=%d", len);
break;
}
}
return count;
}
void
ODM_Write2Byte(
PDM_ODM_T pDM_Odm,
u32 RegAddr,
u16 Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
RTL_W16(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
struct rtw_adapter * Adapter = pDM_Odm->Adapter;
rtw_write16(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
struct rtw_adapter * Adapter = pDM_Odm->Adapter;
PlatformEFIOWrite2Byte(Adapter, RegAddr, Data);
#endif
}
static VOID
_InitNormalChipRegPriority(
IN PADAPTER Adapter,
IN u16 beQ,
IN u16 bkQ,
IN u16 viQ,
IN u16 voQ,
IN u16 mgtQ,
IN u16 hiQ
)
{
u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
_TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
_TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ);
rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
}
VOID
ODM_Write2Byte(
IN PDM_ODM_T pDM_Odm,
IN u4Byte RegAddr,
IN u2Byte Data
)
{
#if(DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
prtl8192cd_priv priv = pDM_Odm->priv;
RTL_W16(RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_CE)
PADAPTER Adapter = pDM_Odm->Adapter;
rtw_write16(Adapter,RegAddr, Data);
#elif(DM_ODM_SUPPORT_TYPE & ODM_MP)
PADAPTER Adapter = pDM_Odm->Adapter;
PlatformEFIOWrite2Byte(Adapter, RegAddr, Data);
#endif
}
ssize_t proc_set_write_reg(struct file *file, const char *buffer, size_t count, loff_t *pos)
{
struct net_device *dev = (struct net_device *)pos;
_adapter *padapter = (_adapter *)rtw_netdev_priv(dev);
char tmp[32];
u32 addr, val, len;
if (count < 3)
{
DBG_8192C("argument size is less than 3\n");
return -EFAULT;
}
len = min(count, sizeof(tmp)-1);
if (buffer && !copy_from_user(tmp, buffer, len)) {
tmp[len] = '\0';
if(sscanf(tmp, "%x %x %x", &addr, &val, &len)!=3) {
DBG_8192C("invalid write_reg parameter!\n");
return -EFAULT;
}
switch(len)
{
case 1:
rtw_write8(padapter, addr, (u8)val);
break;
case 2:
rtw_write16(padapter, addr, (u16)val);
break;
case 4:
rtw_write32(padapter, addr, val);
break;
default:
DBG_8192C("error write length=%d", len);
break;
}
}
return count;
}
void rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe)
{
_irqL irqL;
int t, sz, w_sz, pull=0;
//u8 *mem_addr;
u32 ff_hwaddr;
struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv;
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct tx_desc *ptxdesc;
if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
(pxmitframe->attrib.ether_type != 0x0806) &&
(pxmitframe->attrib.ether_type != 0x888e) &&
(pxmitframe->attrib.dhcp_pkt != 1))
{
rtw_issue_addbareq_cmd(padapter, pxmitframe);
}
//mem_addr = pxmitframe->buf_addr;
RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_dump_xframe()\n"));
for (t = 0; t < pattrib->nr_frags; t++)
{
if (t != (pattrib->nr_frags - 1))
{
RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("pattrib->nr_frags=%d\n", pattrib->nr_frags));
sz = pxmitpriv->frag_len;
sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len);
}
else //no frag
{
sz = pattrib->last_txcmdsz;
}
ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
#ifdef CONFIG_CONCURRENT_MODE
if(!rtw_buddy_adapter_up(padapter))
goto skip_if2_tx;
if(padapter->adapter_type > PRIMARY_ADAPTER)
{
_adapter *pri_adapter = padapter->pbuddy_adapter;
struct dvobj_priv *pri_dvobjpriv = &pri_adapter->dvobjpriv;
_enter_critical(&(pri_dvobjpriv->irq_th_lock), &irqL);
ptxdesc = get_txdesc(pri_adapter, ff_hwaddr);
if(ptxdesc == NULL)
{
_exit_critical(&pri_dvobjpriv->irq_th_lock, &irqL);
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
DBG_8192C("##### Tx desc unavailable !#####\n");
break;
}
update_txdesc(pxmitframe, (uint*)ptxdesc, sz);
rtl8192ce_enqueue_xmitbuf(&(pri_adapter->xmitpriv.tx_ring[ff_hwaddr]), pxmitbuf);
pxmitbuf->len = sz;
w_sz = sz;
wmb();
ptxdesc->txdw0 |= cpu_to_le32(OWN);
_exit_critical(&pri_dvobjpriv->irq_th_lock, &irqL);
rtw_write16(pri_adapter, REG_PCIE_CTRL_REG, ffaddr2dma(ff_hwaddr));
rtw_write_port(padapter, ff_hwaddr, w_sz, (unsigned char*)pxmitbuf);
} else
skip_if2_tx:
#endif
{
_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
ptxdesc = get_txdesc(pxmitframe->padapter, ff_hwaddr);
if(ptxdesc == NULL)
{
_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
DBG_8192C("##### Tx desc unavailable !#####\n");
break;
}
update_txdesc(pxmitframe, (uint*)ptxdesc, sz);
rtl8192ce_enqueue_xmitbuf(&pxmitpriv->tx_ring[ff_hwaddr], pxmitbuf);
pxmitbuf->len = sz;
w_sz = sz;
wmb();
ptxdesc->txdw0 |= cpu_to_le32(OWN);
_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
rtw_write16(padapter, REG_PCIE_CTRL_REG, ffaddr2dma(ff_hwaddr));
rtw_write_port(padapter, ff_hwaddr, w_sz, (unsigned char*)pxmitbuf);
}
rtw_count_tx_stats(padapter, pxmitframe, sz);
RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_write_port, w_sz=%d\n", w_sz));
//DBG_8192C("rtw_write_port, w_sz=%d, sz=%d, txdesc_sz=%d, tid=%d\n", w_sz, sz, w_sz-sz, pattrib->priority);
//mem_addr += w_sz;
//mem_addr = (u8 *)RND4(((SIZE_PTR)(mem_addr)));
}
rtw_free_xmitframe_ex(pxmitpriv, pxmitframe);
}
void rtl8192d_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus)
{
u8 u1JoinBssRptParm[1]={0};
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
BOOLEAN bRecover = _FALSE;
_func_enter_;
DBG_871X("%s\n", __FUNCTION__);
if(mstatus == 1)
{
// We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C.
// Suggested by filen. Added by tynli.
rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid));
// Do not set TSF again here or vWiFi beacon DMA INT will not work.
//rtw_hal_set_hwreg(Adapter, HW_VAR_CORRECT_TSF, (pu1Byte)(&bTypeIbss));
// Hw sequende enable by dedault. 2010.06.23. by tynli.
//set REG_CR bit 8
pHalData->RegCR_1 |= BIT0;
rtw_write8(padapter, REG_CR+1, pHalData->RegCR_1);
// Disable Hw protection for a time which revserd for Hw sending beacon.
// Fix download reserved page packet fail that access collision with the protection time.
// 2010.05.11. Added by tynli.
//SetBcnCtrlReg(Adapter, 0, BIT3);
//SetBcnCtrlReg(Adapter, BIT4, 0);
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(3)));
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4));
// Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.
if(pHalData->RegFwHwTxQCtrl&BIT6)
bRecover = _TRUE;
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl&(~BIT6)));
pHalData->RegFwHwTxQCtrl &= (~BIT6);
SetFwRsvdPagePkt(padapter, 0);
// 2010.05.11. Added by tynli.
//SetBcnCtrlReg(Adapter, BIT3, 0);
//SetBcnCtrlReg(Adapter, 0, BIT4);
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(3));
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(4)));
// To make sure that if there exists an adapter which would like to send beacon.
// If exists, the origianl value of 0x422[6] will be 1, we should check this to
// prevent from setting 0x422[6] to 0 after download reserved page, or it will cause
// the beacon cannot be sent by HW.
// 2010.06.23. Added by tynli.
if(bRecover)
{
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl|BIT6));
pHalData->RegFwHwTxQCtrl |= BIT6;
}
// Clear CR[8] or beacon packet will not be send to TxBuf anymore.
pHalData->RegCR_1 &= (~BIT0);
rtw_write8(padapter, REG_CR+1, pHalData->RegCR_1);
}
SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(u1JoinBssRptParm, mstatus);
FillH2CCmd92D(padapter, H2C_JOINBSSRPT, 1, u1JoinBssRptParm);
_func_exit_;
}
void rtl8188e_set_FwJoinBssReport_cmd(PADAPTER padapter, u8 mstatus)
{
JOINBSSRPT_PARM_88E JoinBssRptParm;
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv);
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
#ifdef CONFIG_WOWLAN
struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
struct sta_info *psta = NULL;
#endif
BOOLEAN bSendBeacon=_FALSE;
BOOLEAN bcn_valid = _FALSE;
u8 DLBcnCount=0;
u32 poll = 0;
_func_enter_;
DBG_871X("%s mstatus(%x)\n", __FUNCTION__,mstatus);
if(mstatus == 1)
{
// We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C.
// Suggested by filen. Added by tynli.
rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid));
// Do not set TSF again here or vWiFi beacon DMA INT will not work.
//correct_TSF(padapter, pmlmeext);
// Hw sequende enable by dedault. 2010.06.23. by tynli.
//rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF));
//rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
//Set REG_CR bit 8. DMA beacon by SW.
pHalData->RegCR_1 |= BIT0;
rtw_write8(padapter, REG_CR+1, pHalData->RegCR_1);
// Disable Hw protection for a time which revserd for Hw sending beacon.
// Fix download reserved page packet fail that access collision with the protection time.
// 2010.05.11. Added by tynli.
//SetBcnCtrlReg(padapter, 0, BIT3);
//SetBcnCtrlReg(padapter, BIT4, 0);
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(3)));
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4));
if(pHalData->RegFwHwTxQCtrl&BIT6)
{
DBG_871X("HalDownloadRSVDPage(): There is an Adapter is sending beacon.\n");
bSendBeacon = _TRUE;
}
// Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame.
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl&(~BIT6)));
pHalData->RegFwHwTxQCtrl &= (~BIT6);
// Clear beacon valid check bit.
rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
DLBcnCount = 0;
poll = 0;
do
{
// download rsvd page.
SetFwRsvdPagePkt(padapter, _FALSE);
DLBcnCount++;
do
{
rtw_yield_os();
//rtw_mdelay_os(10);
// check rsvd page download OK.
rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8*)(&bcn_valid));
poll++;
} while(!bcn_valid && (poll%10)!=0 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
}while(!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
//RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage88ES(): 1 Download RSVD page failed!\n"));
if(padapter->bSurpriseRemoved || padapter->bDriverStopped)
{
}
else if(!bcn_valid)
DBG_871X(ADPT_FMT": 1 DL RSVD page failed! DLBcnCount:%u, poll:%u\n",
ADPT_ARG(padapter) ,DLBcnCount, poll);
else {
struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
pwrctl->fw_psmode_iface_id = padapter->iface_id;
DBG_871X(ADPT_FMT": 1 DL RSVD page success! DLBcnCount:%u, poll:%u\n",
ADPT_ARG(padapter), DLBcnCount, poll);
}
//
// We just can send the reserved page twice during the time that Tx thread is stopped (e.g. pnpsetpower)
// becuase we need to free the Tx BCN Desc which is used by the first reserved page packet.
// At run time, we cannot get the Tx Desc until it is released in TxHandleInterrupt() so we will return
// the beacon TCB in the following code. 2011.11.23. by tynli.
//
//if(bcn_valid && padapter->bEnterPnpSleep)
if(0)
{
if(bSendBeacon)
{
rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
DLBcnCount = 0;
poll = 0;
do
{
SetFwRsvdPagePkt(padapter, _TRUE);
DLBcnCount++;
do
{
rtw_yield_os();
//rtw_mdelay_os(10);
// check rsvd page download OK.
rtw_hal_get_hwreg(padapter, HW_VAR_BCN_VALID, (u8*)(&bcn_valid));
poll++;
} while(!bcn_valid && (poll%10)!=0 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
}while(!bcn_valid && DLBcnCount<=100 && !padapter->bSurpriseRemoved && !padapter->bDriverStopped);
//RT_ASSERT(bcn_valid, ("HalDownloadRSVDPage(): 2 Download RSVD page failed!\n"));
if(padapter->bSurpriseRemoved || padapter->bDriverStopped)
{
}
else if(!bcn_valid)
DBG_871X("%s: 2 Download RSVD page failed! DLBcnCount:%u, poll:%u\n", __FUNCTION__ ,DLBcnCount, poll);
else
DBG_871X("%s: 2 Download RSVD success! DLBcnCount:%u, poll:%u\n", __FUNCTION__, DLBcnCount, poll);
}
}
// Enable Bcn
//SetBcnCtrlReg(padapter, BIT3, 0);
//SetBcnCtrlReg(padapter, 0, BIT4);
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(3));
rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(4)));
// To make sure that if there exists an adapter which would like to send beacon.
// If exists, the origianl value of 0x422[6] will be 1, we should check this to
// prevent from setting 0x422[6] to 0 after download reserved page, or it will cause
// the beacon cannot be sent by HW.
// 2010.06.23. Added by tynli.
if(bSendBeacon)
{
rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl|BIT6));
pHalData->RegFwHwTxQCtrl |= BIT6;
}
//
// Update RSVD page location H2C to Fw.
//
if(bcn_valid)
{
rtw_hal_set_hwreg(padapter, HW_VAR_BCN_VALID, NULL);
DBG_871X("Set RSVD page location to Fw.\n");
//FillH2CCmd88E(Adapter, H2C_88E_RSVDPAGE, H2C_RSVDPAGE_LOC_LENGTH, pMgntInfo->u1RsvdPageLoc);
}
// Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli.
//if(!padapter->bEnterPnpSleep)
{
// Clear CR[8] or beacon packet will not be send to TxBuf anymore.
pHalData->RegCR_1 &= (~BIT0);
rtw_write8(padapter, REG_CR+1, pHalData->RegCR_1);
}
}
#ifdef CONFIG_WOWLAN
if (adapter_to_pwrctl(padapter)->wowlan_mode){
JoinBssRptParm.OpMode = mstatus;
psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(pmlmepriv));
if (psta != NULL) {
JoinBssRptParm.MacID = psta->mac_id;
} else {
JoinBssRptParm.MacID = 0;
}
FillH2CCmd_88E(padapter, H2C_COM_MEDIA_STATUS_RPT, sizeof(JoinBssRptParm), (u8 *)&JoinBssRptParm);
DBG_871X_LEVEL(_drv_info_, "%s opmode:%d MacId:%d\n", __func__, JoinBssRptParm.OpMode, JoinBssRptParm.MacID);
} else {
DBG_871X_LEVEL(_drv_info_, "%s wowlan_mode is off\n", __func__);
}
#endif //CONFIG_WOWLAN
_func_exit_;
}
void sreset_restore_network_station(_adapter *padapter)
{
struct mlme_priv *mlmepriv = &padapter->mlmepriv;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
#if 0
{
//=======================================================
// reset related register of Beacon control
//set MSR to nolink
Set_MSR(padapter, _HW_STATE_NOLINK_);
// reject all data frame
rtw_write16(padapter, REG_RXFLTMAP2,0x00);
//reset TSF
rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
// disable update TSF
SetBcnCtrlReg(padapter, BIT(4), 0);
//=======================================================
}
#endif
rtw_setopmode_cmd(padapter, Ndis802_11Infrastructure);
{
u8 threshold;
#ifdef CONFIG_USB_HCI
// TH=1 => means that invalidate usb rx aggregation
// TH=0 => means that validate usb rx aggregation, use init value.
if(mlmepriv->htpriv.ht_option) {
if(padapter->registrypriv.wifi_spec==1)
threshold = 1;
else
threshold = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
} else {
threshold = 1;
rtw_hal_set_hwreg(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold));
}
#endif
}
set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode);
//disable dynamic functions, such as high power, DIG
//Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE);
rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress);
{
u8 join_type = 0;
rtw_hal_set_hwreg(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type));
}
Set_MSR(padapter, (pmlmeinfo->state & 0x3));
mlmeext_joinbss_event_callback(padapter, 1);
//restore Sequence No.
rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn);
sreset_restore_security_station(padapter);
}
void SetHwReg(_adapter *adapter, HW_VARIABLES variable, u8 *val)
{
HAL_DATA_TYPE *hal_data = GET_HAL_DATA(adapter);
struct dm_priv *dm = &(hal_data->dmpriv);
switch (variable) {
case HW_VAR_DM_FLAG:
dm->DMFlag = *((u8*)val);
break;
case HW_VAR_ENC_BMC_ENABLE:
{
u8 seccfg;
struct security_priv *psecuritypriv = &adapter->securitypriv;
//enable MC/BC hw decrypt
seccfg = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf;
rtw_write8(adapter, REG_SECCFG, seccfg);
break;
}
case HW_VAR_ENC_BMC_DISABLE:
{
struct security_priv *psecuritypriv = &adapter->securitypriv;
rtw_write8(adapter, REG_SECCFG, 0x0c|BIT(5));// enable tx enc and rx dec engine, and no key search for MC/BC
break;
}
case HW_VAR_CHECK_TXBUF:
{
u8 retry_limit;
u16 val16;
u32 reg_200 = 0, reg_204 = 0;
u32 init_reg_200 = 0, init_reg_204 = 0;
u32 start = rtw_get_current_time();
u32 pass_ms;
int i = 0;
retry_limit = 0x01;
val16 = retry_limit << RETRY_LIMIT_SHORT_SHIFT | retry_limit << RETRY_LIMIT_LONG_SHIFT;
rtw_write16(adapter, REG_RL, val16);
while (rtw_get_passing_time_ms(start) < 2000
&& !adapter->bDriverStopped && !adapter->bSurpriseRemoved
) {
reg_200 = rtw_read32(adapter, 0x200);
reg_204 = rtw_read32(adapter, 0x204);
if (i == 0) {
init_reg_200 = reg_200;
init_reg_204 = reg_204;
}
i++;
if ((reg_200 & 0x00ffffff) != (reg_204 & 0x00ffffff)) {
//DBG_871X("%s: (HW_VAR_CHECK_TXBUF)TXBUF NOT empty - 0x204=0x%x, 0x200=0x%x (%d)\n", __FUNCTION__, reg_204, reg_200, i);
rtw_msleep_os(10);
} else {
break;
}
}
pass_ms = rtw_get_passing_time_ms(start);
if (adapter->bDriverStopped || adapter->bSurpriseRemoved) {
} else if (pass_ms >= 2000 || (reg_200 & 0x00ffffff) != (reg_204 & 0x00ffffff)) {
DBG_871X_LEVEL(_drv_always_, "%s:(HW_VAR_CHECK_TXBUF)NOT empty(%d) in %d ms\n", __FUNCTION__, i, pass_ms);
DBG_871X_LEVEL(_drv_always_, "%s:(HW_VAR_CHECK_TXBUF)0x200=0x%08x, 0x204=0x%08x (0x%08x, 0x%08x)\n",
__FUNCTION__, reg_200, reg_204, init_reg_200, init_reg_204);
//rtw_warn_on(1);
} else {
DBG_871X("%s:(HW_VAR_CHECK_TXBUF)TXBUF Empty(%d) in %d ms\n", __FUNCTION__, i, pass_ms);
}
retry_limit = 0x30;
val16 = retry_limit << RETRY_LIMIT_SHORT_SHIFT | retry_limit << RETRY_LIMIT_LONG_SHIFT;
rtw_write16(adapter, REG_RL, val16);
}
break;
default:
if(0)
DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HW_VARIABLES(%d) not defined!\n", __FUNCTION__, variable);
break;
}
}
void SetHwReg(struct adapter *adapter, u8 variable, u8 *val)
{
struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
DM_ODM_T *odm = &(hal_data->odmpriv);
switch (variable) {
case HW_VAR_PORT_SWITCH:
hw_var_port_switch(adapter);
break;
case HW_VAR_INIT_RTS_RATE:
rtw_warn_on(1);
break;
case HW_VAR_SEC_CFG:
{
u16 reg_scr;
reg_scr = rtw_read16(adapter, REG_SECCFG);
rtw_write16(adapter, REG_SECCFG, reg_scr|SCR_CHK_KEYID|SCR_RxDecEnable|SCR_TxEncEnable);
}
break;
case HW_VAR_SEC_DK_CFG:
{
struct security_priv *sec = &adapter->securitypriv;
u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
if (val) { /* Enable default key related setting */
reg_scr |= SCR_TXBCUSEDK;
if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
reg_scr |= (SCR_RxUseDK|SCR_TxUseDK);
} else /* Disable default key related setting */
reg_scr &= ~(SCR_RXBCUSEDK|SCR_TXBCUSEDK|SCR_RxUseDK|SCR_TxUseDK);
rtw_write8(adapter, REG_SECCFG, reg_scr);
}
break;
case HW_VAR_DM_FLAG:
odm->SupportAbility = *((u32 *)val);
break;
case HW_VAR_DM_FUNC_OP:
if (*((u8 *)val) == true) {
/* save dm flag */
odm->BK_SupportAbility = odm->SupportAbility;
} else {
/* restore dm flag */
odm->SupportAbility = odm->BK_SupportAbility;
}
break;
case HW_VAR_DM_FUNC_SET:
if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
struct dm_priv *dm = &hal_data->dmpriv;
dm->DMFlag = dm->InitDMFlag;
odm->SupportAbility = dm->InitODMFlag;
} else {
odm->SupportAbility |= *((u32 *)val);
}
break;
case HW_VAR_DM_FUNC_CLR:
/*
* input is already a mask to clear function
* don't invert it again! George, Lucas@20130513
*/
odm->SupportAbility &= *((u32 *)val);
break;
case HW_VAR_AMPDU_MIN_SPACE:
/* TODO - Is something needed here? */
break;
case HW_VAR_WIRELESS_MODE:
/* TODO - Is something needed here? */
break;
default:
DBG_871X_LEVEL(
_drv_always_,
FUNC_ADPT_FMT" variable(%d) not defined!\n",
FUNC_ADPT_ARG(adapter),
variable
);
break;
}
}
s32
MPT_InitializeAdapter(
IN PADAPTER pAdapter,
IN u8 Channel
)
{
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
s32 rtStatus = _SUCCESS;
PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx;
u32 ledsetting;
struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv;
//-------------------------------------------------------------------------
// HW Initialization for 8190 MPT.
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// SW Initialization for 8190 MP.
//-------------------------------------------------------------------------
pMptCtx->bMptDrvUnload = _FALSE;
pMptCtx->bMassProdTest = _FALSE;
pMptCtx->bMptIndexEven = _TRUE; //default gain index is -6.0db
pMptCtx->h2cReqNum = 0x0;
/* Init mpt event. */
#if 0 // for Windows
NdisInitializeEvent( &(pMptCtx->MptWorkItemEvent) );
NdisAllocateSpinLock( &(pMptCtx->MptWorkItemSpinLock) );
PlatformInitializeWorkItem(
Adapter,
&(pMptCtx->MptWorkItem),
(RT_WORKITEM_CALL_BACK)MPT_WorkItemCallback,
(PVOID)Adapter,
"MptWorkItem");
#endif
//init for BT MP
#ifdef CONFIG_RTL8723A
pMptCtx->bMPh2c_timeout = _FALSE;
pMptCtx->MptH2cRspEvent = _FALSE;
pMptCtx->MptBtC2hEvent = _FALSE;
_rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
_init_timer( &pMptCtx->MPh2c_timeout_timer, pAdapter->pnetdev, MPh2c_timeout_handle, pAdapter );
//before the reset bt patch command,set the wifi page 0's IO to BT mac reboot.
#endif
pMptCtx->bMptWorkItemInProgress = _FALSE;
pMptCtx->CurrMptAct = NULL;
//-------------------------------------------------------------------------
#if 1
// Don't accept any packets
rtw_write32(pAdapter, REG_RCR, 0);
#else
// Accept CRC error and destination address
//pHalData->ReceiveConfig |= (RCR_ACRC32|RCR_AAP);
//rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
rtw_write32(pAdapter, REG_RCR, 0x70000101);
#endif
#if 0
// If EEPROM or EFUSE is empty,we assign as RF 2T2R for MP.
if (pHalData->AutoloadFailFlag == TRUE)
{
pHalData->RF_Type = RF_2T2R;
}
#endif
//ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
//rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS);
if(IS_HARDWARE_TYPE_8192DU(pAdapter))
{
rtw_write32(pAdapter, REG_LEDCFG0, 0x8888);
}
else
{
//rtw_write32(pAdapter, REG_LEDCFG0, 0x08080);
ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
#if defined (CONFIG_RTL8192C) || defined( CONFIG_RTL8192D )
rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS);
#endif
}
PHY_IQCalibrate(pAdapter, _FALSE);
dm_CheckTXPowerTracking(&pHalData->odmpriv); //trigger thermal meter
PHY_LCCalibrate(pAdapter);
#ifdef CONFIG_PCI_HCI
PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //Wifi default use Main
#else
#ifdef CONFIG_RTL8192C
if (pHalData->BoardType == BOARD_MINICARD)
PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //default use Main
#endif
#endif
pMptCtx->backup0xc50 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
pMptCtx->backup0xc58 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
pMptCtx->backup0xc30 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
#ifdef CONFIG_RTL8188E
pMptCtx->backup0x52_RF_A = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
pMptCtx->backup0x52_RF_B = (u1Byte)PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
#endif
//set ant to wifi side in mp mode
#ifdef CONFIG_RTL8723A
rtl8723a_InitAntenna_Selection(pAdapter);
#endif //CONFIG_RTL8723A
//set ant to wifi side in mp mode
rtw_write16(pAdapter, 0x870, 0x300);
rtw_write16(pAdapter, 0x860, 0x110);
if (pAdapter->registrypriv.mp_mode == 1)
pmlmepriv->fw_state = WIFI_MP_STATE;
return rtStatus;
}
// 1: write RCR DATA BIT
// 2: issue peer traffic indication
// 3: go back to the channel linked with AP, terminating channel switch procedure
// 4: init channel sensing, receive all data and mgnt frame
// 5: channel sensing and report candidate channel
// 6: first time set channel to off channel
// 7: go back tp the channel linked with AP when set base channel as target channel
void TDLS_option_workitem_callback(struct work_struct *work)
{
struct sta_info *ptdls_sta = container_of(work, struct sta_info, option_workitem);
_adapter *padapter = ptdls_sta->padapter;
struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info;
u32 bit_6=1<<6, bit_7=1<<7, bit_4=1<<4;
u8 survey_channel, i, min;
switch(ptdls_sta->option){
case 1:
//As long as TDLS handshake success, we should set RCR_CBSSID_DATA bit to 0
//such we can receive all kinds of data frames.
rtw_write32(padapter, 0x0608, rtw_read32(padapter, 0x0608)&(~bit_6));
DBG_8192C("wirte 0x0608, set bit6 off\n");
break;
case 2:
issue_tdls_peer_traffic_indication(padapter, ptdls_sta);
break;
case 3:
_cancel_timer_ex(&ptdls_sta->base_ch_timer);
_cancel_timer_ex(&ptdls_sta->off_ch_timer);
SelectChannel(padapter, pmlmeext->cur_channel);
ptdls_sta->state &= ~(TDLS_CH_SWITCH_ON_STATE |
TDLS_PEER_AT_OFF_STATE |
TDLS_AT_OFF_CH_STATE);
DBG_8192C("go back to base channel\n ");
issue_nulldata(padapter, 0);
break;
case 4:
rtw_write32(padapter, 0x0608, rtw_read32(padapter, 0x0608)&(~bit_6)&(~bit_7));
rtw_write16(padapter, 0x06A4,0xffff); //maybe don't need to write here
//disable update TSF
rtw_write8(padapter, 0x0550, rtw_read8(padapter, 0x0550)|bit_4);
pmlmeext->sitesurvey_res.channel_idx = 0;
ptdls_sta->option = 5;
_set_workitem(&ptdls_sta->option_workitem);
break;
case 5:
survey_channel = pmlmeext->channel_set[pmlmeext->sitesurvey_res.channel_idx].ChannelNum;
if(survey_channel){
SelectChannel(padapter, survey_channel);
pmlmeinfo->tdls_cur_channel = survey_channel;
pmlmeext->sitesurvey_res.channel_idx++;
_set_timer(&ptdls_sta->option_timer, SURVEY_TO);
}else{
SelectChannel(padapter, pmlmeext->cur_channel);
//enable update TSF
rtw_write8(padapter, 0x0550, rtw_read8(padapter, 0x0550)&(~bit_4));
rtw_write32(padapter, 0x0608, rtw_read32(padapter, 0x0608)|(bit_7));
if(pmlmeinfo->tdls_ch_sensing==1){
pmlmeinfo->tdls_ch_sensing=0;
pmlmeinfo->tdls_cur_channel=1;
min=pmlmeinfo->tdls_collect_pkt_num[0];
for(i=1; i<14-1; i++){
if(min > pmlmeinfo->tdls_collect_pkt_num[i]){
pmlmeinfo->tdls_cur_channel=i+1;
min=pmlmeinfo->tdls_collect_pkt_num[i];
}
pmlmeinfo->tdls_collect_pkt_num[i]=0;
}
pmlmeinfo->tdls_collect_pkt_num[0]=0;
pmlmeinfo->tdls_candidate_ch=pmlmeinfo->tdls_cur_channel;
DBG_8192C("TDLS channel sensing done, candidate channel: %02x\n", pmlmeinfo->tdls_candidate_ch);
pmlmeinfo->tdls_cur_channel=0;
}
if(ptdls_sta->state & TDLS_PEER_SLEEP_STATE){
ptdls_sta->state |= TDLS_APSD_CHSW_STATE;
}else{
//send null data with pwrbit==1 before send ch_switching_req to peer STA.
issue_nulldata(padapter, 1);
ptdls_sta->state |= TDLS_CH_SW_INITIATOR_STATE;
issue_tdls_ch_switch_req(padapter, ptdls_sta->hwaddr);
DBG_8192C("issue tdls ch switch req\n");
}
}
break;
case 6:
issue_nulldata(padapter, 1);
SelectChannel(padapter, ptdls_sta->off_ch);
DBG_8192C("change channel to tar ch:%02x\n", ptdls_sta->off_ch);
ptdls_sta->state |= TDLS_AT_OFF_CH_STATE;
ptdls_sta->state &= ~(TDLS_PEER_AT_OFF_STATE);
_set_timer(&ptdls_sta->option_timer, (u32)ptdls_sta->ch_switch_time);
break;
case 7:
_cancel_timer_ex(&ptdls_sta->base_ch_timer);
_cancel_timer_ex(&ptdls_sta->off_ch_timer);
SelectChannel(padapter, pmlmeext->cur_channel);
ptdls_sta->state &= ~(TDLS_CH_SWITCH_ON_STATE |
TDLS_PEER_AT_OFF_STATE |
TDLS_AT_OFF_CH_STATE);
DBG_8192C("go back to base channel\n ");
issue_nulldata(padapter, 0);
_set_timer(&ptdls_sta->option_timer, (u32)ptdls_sta->ch_switch_time);
break;
}
}
s32 rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe)
{
s32 ret = _SUCCESS;
s32 inner_ret = _SUCCESS;
_irqL irqL;
int t, sz, w_sz, pull=0;
//u8 *mem_addr;
u32 ff_hwaddr;
struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf;
struct pkt_attrib *pattrib = &pxmitframe->attrib;
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
struct security_priv *psecuritypriv = &padapter->securitypriv;
struct tx_desc *ptxdesc;
if ((pxmitframe->frame_tag == DATA_FRAMETAG) &&
(pxmitframe->attrib.ether_type != 0x0806) &&
(pxmitframe->attrib.ether_type != 0x888e) &&
(pxmitframe->attrib.dhcp_pkt != 1))
{
rtw_issue_addbareq_cmd(padapter, pxmitframe);
}
//mem_addr = pxmitframe->buf_addr;
RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_dump_xframe()\n"));
for (t = 0; t < pattrib->nr_frags; t++)
{
if (inner_ret != _SUCCESS && ret == _SUCCESS)
ret = _FAIL;
if (t != (pattrib->nr_frags - 1))
{
RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("pattrib->nr_frags=%d\n", pattrib->nr_frags));
sz = pxmitpriv->frag_len;
sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len);
}
else //no frag
{
sz = pattrib->last_txcmdsz;
}
ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe);
_enter_critical(&pdvobjpriv->irq_th_lock, &irqL);
ptxdesc = get_txdesc(pxmitframe, ff_hwaddr);
if(ptxdesc == NULL)
{
_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
rtw_free_xmitbuf(pxmitpriv, pxmitbuf);
DBG_8192C("##### Tx desc unavailable !#####\n");
break;
}
update_txdesc(pxmitframe, (uint*)ptxdesc, sz);
rtl8192de_enqueue_xmitbuf(&pxmitpriv->tx_ring[ff_hwaddr], pxmitbuf);
pxmitbuf->len = sz;
_exit_critical(&pdvobjpriv->irq_th_lock, &irqL);
w_sz = sz;
rtw_write16(padapter, REG_PCIE_CTRL_REG, ffaddr2dma(ff_hwaddr));
inner_ret = rtw_write_port(padapter, ff_hwaddr, w_sz, (unsigned char*)pxmitbuf);
rtw_count_tx_stats(padapter, pxmitframe, sz);
RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_write_port, w_sz=%d\n", w_sz));
//DBG_8192C("rtw_write_port, w_sz=%d, sz=%d, txdesc_sz=%d, tid=%d\n", w_sz, sz, w_sz-sz, pattrib->priority);
//mem_addr += w_sz;
//mem_addr = (u8 *)RND4(((SIZE_PTR)(mem_addr)));
}
rtw_free_xmitframe(pxmitpriv, pxmitframe);
if (ret != _SUCCESS)
rtw_sctx_done_err(&pxmitbuf->sctx, RTW_SCTX_DONE_UNKNOWN);
return ret;
}
