static int s2m_get_voltage_sel_regmap(struct regulator_dev *rdev)
{
struct s2mps16_info *s2mps16 = rdev_get_drvdata(rdev);
int ret, reg_id = rdev_get_id(rdev);
unsigned int val;
/* if dvs pin set high, get the voltage on the diffrent register. */
if (reg_id == S2MPS16_BUCK6
&& s2mps16->dvs_en && s2m_get_dvs_is_on()) {
ret = sec_reg_read(s2mps16->iodev, S2MPS16_REG_B6CTRL2, &val);
if (ret)
return ret;
} else if ((reg_id >= S2MPS16_BUCK1 && reg_id <= S2MPS16_BUCK5)
&& s2mps16->vsel_value[reg_id] && s2mps16->cache_data) {
return s2mps16->vsel_value[reg_id];
} else {
ret = sec_reg_read(s2mps16->iodev, rdev->desc->vsel_reg, &val);
if (ret)
return ret;
}
val &= rdev->desc->vsel_mask;
return val;
}
int gpu_register_dump(void)
{
if (gpu_is_power_on() && !s2m_get_dvs_is_on()) {
/* MCS Value check */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x10051224 , __raw_readl(EXYNOS7420_VA_SYSREG + 0x1224),
"REG_DUMP: G3D_EMA_RF2_UHD_CON %x\n", __raw_readl(EXYNOS7420_VA_SYSREG + 0x1224));
/* G3D PMU */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x105C4100, __raw_readl(EXYNOS_PMU_G3D_CONFIGURATION),
"REG_DUMP: EXYNOS_PMU_G3D_CONFIGURATION %x\n", __raw_readl(EXYNOS_PMU_G3D_CONFIGURATION));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x105C4104, __raw_readl(EXYNOS_PMU_G3D_STATUS),
"REG_DUMP: EXYNOS_PMU_G3D_STATUS %x\n", __raw_readl(EXYNOS_PMU_G3D_STATUS));
/* G3D PLL */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x105C6100, __raw_readl(EXYNOS_PMU_GPU_DVS_CTRL),
"REG_DUMP: EXYNOS_PMU_GPU_DVS_CTRL %x\n", __raw_readl(EXYNOS_PMU_GPU_DVS_CTRL));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x10576104, __raw_readl(EXYNOS_PMU_GPU_DVS_STATUS),
"REG_DUMP: GPU_DVS_STATUS %x\n", __raw_readl(EXYNOS_PMU_GPU_DVS_STATUS));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x10051234, __raw_readl(EXYNOS7420_VA_SYSREG + 0x1234),
"REG_DUMP: G3D_G3DCFG_REG0 %x\n", __raw_readl(EXYNOS7420_VA_SYSREG + 0x1234));
#ifdef CONFIG_EXYNOS_NOC_DEBUGGING
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14A002F0, __raw_readl(g3d0_outstanding_regs + 0x2F0),
"REG_DUMP: read outstanding %x\n", __raw_readl(g3d0_outstanding_regs + 0x2F0));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14A003F0, __raw_readl(g3d0_outstanding_regs + 0x3F0),
"REG_DUMP: write outstanding %x\n", __raw_readl(g3d0_outstanding_regs + 0x3F0));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14A202F0, __raw_readl(g3d1_outstanding_regs + 0x2F0),
"REG_DUMP: read outstanding %x\n", __raw_readl(g3d1_outstanding_regs + 0x2F0));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14A203F0, __raw_readl(g3d1_outstanding_regs + 0x3F0),
"REG_DUMP: write outstanding %x\n", __raw_readl(g3d1_outstanding_regs + 0x3F0));
#endif /* CONFIG_EXYNOS_NOC_DEBUGGING */
/* G3D PLL */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0000, __raw_readl(G3D_LOCK),
"REG_DUMP: EXYNOS7420_G3D_PLL_LOCK %x\n", __raw_readl(G3D_LOCK));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0100, __raw_readl(G3D_CON),
"REG_DUMP: EXYNOS7420_G3D_PLL_CON0 %x\n", __raw_readl(G3D_CON));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0104, __raw_readl(G3D_CON1),
"REG_DUMP: EXYNOS7420_G3D_PLL_CON1 %x\n", __raw_readl(G3D_CON1));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0108, __raw_readl(G3D_CON2),
"REG_DUMP: EXYNOS7420_G3D_PLL_CON2 %x\n", __raw_readl(G3D_CON2));
/* G3D SRC */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0200, __raw_readl(EXYNOS7420_MUX_SEL_G3D),
"REG_DUMP: EXYNOS7420_SRC_SEL_G3D %x\n", __raw_readl(EXYNOS7420_MUX_SEL_G3D));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0300, __raw_readl(EXYNOS7420_MUX_ENABLE_G3D),
"REG_DUMP: EXYNOS7420_SRC_ENABLE_G3D %x\n", __raw_readl(EXYNOS7420_MUX_ENABLE_G3D));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0400, __raw_readl(EXYNOS7420_MUX_STAT_G3D),
"REG_DUMP: EXYNOS7420_SRC_STAT_G3D %x\n", __raw_readl(EXYNOS7420_MUX_STAT_G3D));
/* G3D DIV */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0600, __raw_readl(EXYNOS7420_DIV_G3D),
"REG_DUMP: EXYNOS7420_DIV_G3D %x\n", __raw_readl(EXYNOS7420_DIV_G3D));
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0700, __raw_readl(EXYNOS7420_DIV_STAT_G3D),
"REG_DUMP: EXYNOS7420_DIV_STAT_G3D %x\n", __raw_readl(EXYNOS7420_DIV_STAT_G3D));
/* G3D ENABLE */
GPU_LOG(DVFS_WARNING, LSI_REGISTER_DUMP, 0x14AA0B00, __raw_readl(EXYNOS7420_CLK_ENABLE_IP_G3D),
"REG_DUMP: EXYNOS7420_ENABLE_IP_G3D %x\n", __raw_readl(EXYNOS7420_CLK_ENABLE_IP_G3D));
} else {
GPU_LOG(DVFS_WARNING, DUMMY, 0u, 0u, "%s: Power Status %d, DVS Status %d\n", __func__, gpu_is_power_on(), s2m_get_dvs_is_on());
}
return 0;
}
static int s2m_set_voltage_sel_regmap_buck(struct regulator_dev *rdev,
unsigned sel)
{
int ret;
struct s2mps16_info *s2mps16 = rdev_get_drvdata(rdev);
int reg_id = rdev_get_id(rdev);
unsigned int voltage;
char name[16];
int buck2_set_val, delta_val;
/* If dvs_en = 0, dvs_pin = 1, occur BUG_ON */
if (reg_id == S2MPS16_BUCK6
&& !s2mps16->dvs_en && gpio_is_valid(s2mps16->dvs_pin)) {
BUG_ON(s2m_get_dvs_is_on());
}
/* Save cached mode buffer */
if (reg_id == S2MPS16_BUCK1 || reg_id == S2MPS16_BUCK3)
s2mps16->vsel_value[reg_id] = sel;
if ((reg_id == S2MPS16_BUCK2 || reg_id == S2MPS16_BUCK4 ||
reg_id == S2MPS16_BUCK5) && !s2mps16->buck_dvs_on)
s2mps16->vsel_value[reg_id] = sel;
/* BUCK2 Control */
if (reg_id == S2MPS16_BUCK2 && s2mps16->buck_dvs_on) {
mutex_lock(&s2mps16->lock);
if (s2mps16->buck2_dvs == 0)
delta_val = 100000;
else if (s2mps16->buck2_dvs == 1)
delta_val = 0;
else if (s2mps16->buck2_dvs == 2)
delta_val = 75000;
else if (s2mps16->buck2_dvs == 3)
delta_val = 50000;
else
delta_val = 0;
buck2_set_val = rdev->desc->min_uV + (rdev->desc->uV_step * sel);
if (delta_val + buck2_set_val <= BUCK2_ASV_MAX) {
if (!s2mps16->buck2_sync) {
ret = s2m_set_fix_ldo_voltage(rdev, 1);
if (ret < 0)
goto out;
}
} else {
if (s2mps16->buck2_sync) {
ret = s2m_set_fix_ldo_voltage(rdev, 0);
if (ret < 0)
goto out;
}
}
snprintf(name, sizeof(name), "BUCK%d", (reg_id - S2MPS16_BUCK1) + 1);
voltage = (sel * S2MPS16_BUCK_STEP1) + S2MPS16_BUCK_MIN1;
exynos_ss_regulator(name, rdev->desc->vsel_reg, voltage, ESS_FLAG_IN);
s2mps16->vsel_value[reg_id] = sel;
ret = sec_reg_write(s2mps16->iodev, rdev->desc->vsel_reg, sel);
if (ret < 0)
goto out;
exynos_ss_regulator(name, rdev->desc->vsel_reg, voltage, ESS_FLAG_OUT);
mutex_unlock(&s2mps16->lock);
return ret;
}
if ((reg_id == S2MPS16_BUCK4 || reg_id == S2MPS16_BUCK5) && s2mps16->buck_dvs_on) {
mutex_lock(&s2mps16->lock);
ret = s2m_set_max_int_voltage(rdev, sel);
if (ret < 0)
goto out;
mutex_unlock(&s2mps16->lock);
return ret;
}
/* voltage information logging to snapshot feature */
snprintf(name, sizeof(name), "BUCK%d", (reg_id - S2MPS16_BUCK1) + 1);
if (reg_id == S2MPS16_BUCK8 || reg_id == S2MPS16_BUCK9){
voltage = (sel * S2MPS16_BUCK_STEP2) + S2MPS16_BUCK_MIN2;
dev_info(&rdev->dev, ":BUCK%d voltage :%d \n",
(reg_id - S2MPS16_BUCK1) + 1, voltage);
} else
voltage = (sel * S2MPS16_BUCK_STEP1) + S2MPS16_BUCK_MIN1;
exynos_ss_regulator(name, rdev->desc->vsel_reg, voltage, ESS_FLAG_IN);
ret = sec_reg_write(s2mps16->iodev, rdev->desc->vsel_reg, sel);
if (ret < 0)
goto i2c_out;
exynos_ss_regulator(name, rdev->desc->vsel_reg, voltage, ESS_FLAG_OUT);
if (rdev->desc->apply_bit)
ret = sec_reg_update(s2mps16->iodev, rdev->desc->apply_reg,
rdev->desc->apply_bit,
rdev->desc->apply_bit);
return ret;
out:
mutex_unlock(&s2mps16->lock);
i2c_out:
pr_warn("%s: failed to set voltage_sel_regmap\n", rdev->desc->name);
exynos_ss_regulator(name, rdev->desc->vsel_reg, voltage, ESS_FLAG_ON);
return ret;
}
