void __init exynos_init_io(struct map_desc *mach_desc, int size) { struct map_desc *iodesc = exynos_iodesc; int iodesc_sz = ARRAY_SIZE(exynos_iodesc); #if defined(CONFIG_OF) && defined(CONFIG_ARCH_EXYNOS5) unsigned long root = of_get_flat_dt_root(); /* initialize the io descriptors we need for initialization */ if (of_flat_dt_is_compatible(root, "samsung,exynos5440")) { iodesc = exynos5440_iodesc; iodesc_sz = ARRAY_SIZE(exynos5440_iodesc); } #endif debug_ll_io_init(); iotable_init(iodesc, iodesc_sz); if (mach_desc) iotable_init(mach_desc, size); /* detect cpu id and rev. */ s5p_init_cpu(S5P_VA_CHIPID); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); /* TO support Watch dog reset */ wdt_reset_init(); /* Setup platform-specific resume code */ s5p_resume_cpu_id = samsung_cpu_id; plat_cpu_resume = s3c_cpu_resume; }
void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) { unsigned long idcode; /* initialise the io descriptors we need for initialisation */ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); iotable_init(mach_desc, size); idcode = __raw_readl(S3C_VA_SYS + 0x118); s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); }
void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) { /* initialise the io descriptors we need for initialisation */ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); iotable_init(mach_desc, size); /* detect cpu id */ s3c64xx_init_cpu(); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); }
void __init s5p64xx_init_io(struct map_desc *mach_desc, int size) { unsigned long idcode; /* initialise the io descriptors we need for initialisation */ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); iotable_init(mach_desc, size); idcode = 0xABABAB00; s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); }
void __init exynos_init_io(struct map_desc *mach_desc, int size) { /* initialize the io descriptors we need for initialization */ iotable_init(exynos_iodesc, ARRAY_SIZE(exynos_iodesc)); if (mach_desc) iotable_init(mach_desc, size); /* detect cpu id and rev. */ s5p_init_cpu(S5P_VA_CHIPID); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); }
void __init s5pv210_init_io(struct map_desc *mach_desc, int size) { /* */ iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc)); if (mach_desc) iotable_init(mach_desc, size); /* */ s5p_init_cpu(S5P_VA_CHIPID); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); }
void __init s5p_init_io(struct map_desc *mach_desc, int size, void __iomem *cpuid_addr) { unsigned long idcode; /* initialize the io descriptors we need for initialization */ iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc)); if (mach_desc) iotable_init(mach_desc, size); idcode = __raw_readl(cpuid_addr); s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); }
void __init s5p_init_io(struct map_desc *mach_desc, int size, void __iomem *cpuid_addr) { /* initialize the io descriptors we need for initialization */ iotable_init(s5p_iodesc, ARRAY_SIZE(s5p_iodesc)); if (mach_desc) iotable_init(mach_desc, size); /* detect cpu id and rev. */ s5p_init_cpu(cpuid_addr); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); }
void __init s5pc11x_init_io(struct map_desc *mach_desc, int size) { unsigned long idcode; /* initialise the io descriptors we need for initialisation */ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); iotable_init(mach_desc, size); idcode = __raw_readl(S5PC11X_VA_CHIPID); arm_pm_restart = s5pc11x_pm_restart; s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); }
void __init s5p64x0_init_io(struct map_desc *mach_desc, int size) { /* initialize the io descriptors we need for initialization */ iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); if (mach_desc) iotable_init(mach_desc, size); /* detect cpu id and rev. */ s5p_init_cpu(S5P64X0_SYS_ID); s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); samsung_wdt_reset_init(S3C_VA_WATCHDOG); }
void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) { unsigned long idcode = 0x0; /* initialise the io descriptors we need for initialisation */ iotable_init(mach_desc, size); iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); if (cpu_architecture() >= CPU_ARCH_ARMv5) { idcode = s3c24xx_read_idcode_v5(); } else { idcode = s3c24xx_read_idcode_v4(); } arm_pm_restart = s3c24xx_pm_restart; s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); }
void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) { unsigned long idcode; /* initialise the io descriptors we need for initialisation */ iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); iotable_init(mach_desc, size); idcode = __raw_readl(S3C_VA_SYS + 0x118); if (!idcode) { /* S3C6400 has the ID register in a different place, * and needs a write before it can be read. */ __raw_writel(0x0, S3C_VA_SYS + 0xA1C); idcode = __raw_readl(S3C_VA_SYS + 0xA1C); } s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids)); }