void s5p_mfc_clock_off(struct s5p_mfc_dev *dev)
{
int state, val;
unsigned long timeout, flags;
int ret = 0;
if (IS_MFCV6(dev)) {
spin_lock_irqsave(&dev->pm.clklock, flags);
if ((atomic_dec_return(&dev->clk_ref) == 0) &&
FW_HAS_BUS_RESET(dev)) {
s5p_mfc_write_reg(dev, 0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);
timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
/* Check bus status */
do {
if (time_after(jiffies, timeout)) {
mfc_err_dev("Timeout while resetting MFC.\n");
break;
}
val = s5p_mfc_read_reg(dev,
S5P_FIMV_MFC_BUS_RESET_CTRL);
} while ((val & 0x2) == 0);
}
spin_unlock_irqrestore(&dev->pm.clklock, flags);
} else {
atomic_dec_return(&dev->clk_ref);
}
state = atomic_read(&dev->clk_ref);
if (state < 0) {
mfc_err_dev("Clock state is wrong(%d)\n", state);
atomic_set(&dev->clk_ref, 0);
} else {
if (dev->curr_ctx_drm && dev->is_support_smc) {
mfc_debug(3, "Begin: disable protection\n");
spin_lock_irqsave(&dev->pm.clklock, flags);
ret = exynos_smc(SMC_PROTECTION_SET, 0,
dev->id, SMC_PROTECTION_DISABLE);
if (!ret) {
printk("Protection Disable failed! ret(%u)\n", ret);
spin_unlock_irqrestore(&dev->pm.clklock, flags);
clk_disable(dev->pm.clock);
return;
}
mfc_debug(3, "End: disable protection\n");
spin_unlock_irqrestore(&dev->pm.clklock, flags);
} else {
s5p_mfc_mem_suspend(dev->alloc_ctx[0]);
}
clk_disable(dev->pm.clock);
}
mfc_debug(2, "- %d\n", state);
}
void s5p_mfc_clock_off(void)
{
struct s5p_mfc_dev *dev = platform_get_drvdata(to_platform_device(pm->device));
atomic_dec(&clk_ref);
#ifdef CLK_DEBUG
mfc_debug(3, "- %d", atomic_read(&clk_ref));
#endif
if (atomic_read(&clk_ref) == 0)
s5p_mfc_mem_suspend(dev->alloc_ctx[0]);
clk_disable(pm->clock);
}
void s5p_mfc_clock_off(void)
{
int state, val;
unsigned long timeout, flags;
struct s5p_mfc_dev *dev = platform_get_drvdata(to_platform_device(pm->device));
if (IS_MFCV6(dev)) {
spin_lock_irqsave(&pm->clklock, flags);
if ((atomic_dec_return(&clk_ref) == 0) &&
FW_HAS_BUS_RESET(dev)) {
s5p_mfc_write_reg(0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);
timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
/* Check bus status */
do {
if (time_after(jiffies, timeout)) {
mfc_err("Timeout while resetting MFC.\n");
break;
}
val = s5p_mfc_read_reg(
S5P_FIMV_MFC_BUS_RESET_CTRL);
} while ((val & 0x2) == 0);
}
spin_unlock_irqrestore(&pm->clklock, flags);
} else {
atomic_dec_return(&clk_ref);
}
state = atomic_read(&clk_ref);
if (state < 0) {
mfc_err("Clock state is wrong(%d)\n", state);
atomic_set(&clk_ref, 0);
} else {
if (!dev->curr_ctx_drm)
s5p_mfc_mem_suspend(dev->alloc_ctx[0]);
clk_disable(pm->clock);
}
}
int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
{
enum mfc_buf_usage_type buf_type;
int ret;
mfc_debug_enter();
if (!dev) {
mfc_err("no mfc device to run\n");
return -EINVAL;
}
mfc_info_dev("curr_ctx_drm:%d\n", dev->curr_ctx_drm);
dev->wakeup_status = 1;
/* Set clock source again after wake up */
s5p_mfc_set_clock_parent(dev);
/* 0. MFC reset */
mfc_debug(2, "MFC reset...\n");
s5p_mfc_clock_on(dev);
dev->wakeup_status = 0;
/* SYSMMU default block mode (not enalble/disable) */
if (dev->curr_ctx_drm) {
ret = s5p_mfc_mem_resume(dev->alloc_ctx[0]);
if (ret < 0)
mfc_err_dev("Failed to attach iommu\n");
s5p_mfc_mem_suspend(dev->alloc_ctx[0]);
}
ret = s5p_mfc_reset(dev);
if (ret) {
mfc_err_dev("Failed to reset MFC - timeout.\n");
goto err_mfc_wakeup;
}
mfc_debug(2, "Done MFC reset...\n");
if (dev->curr_ctx_drm)
buf_type = MFCBUF_DRM;
else
buf_type = MFCBUF_NORMAL;
/* 1. Set DRAM base Addr */
s5p_mfc_init_memctrl(dev, buf_type);
/* 2. Initialize registers of channel I/F */
s5p_mfc_clear_cmds(dev);
s5p_mfc_clean_dev_int_flags(dev);
/* 3. Initialize firmware */
if (!FW_WAKEUP_AFTER_RISC_ON(dev))
ret = s5p_mfc_wakeup_cmd(dev);
if (ret) {
mfc_err_dev("Failed to send command to MFC - timeout.\n");
goto err_mfc_wakeup;
}
/* 4. Release reset signal to the RISC */
if (IS_MFCV6(dev))
s5p_mfc_write_reg(dev, 0x1, S5P_FIMV_RISC_ON);
else
s5p_mfc_write_reg(dev, 0x3ff, S5P_FIMV_SW_RESET);
mfc_debug(2, "Will now wait for completion of firmware transfer.\n");
if (FW_WAKEUP_AFTER_RISC_ON(dev)) {
if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_FW_STATUS_RET)) {
mfc_err_dev("Failed to load firmware.\n");
s5p_mfc_clean_dev_int_flags(dev);
ret = -EIO;
goto err_mfc_wakeup;
}
}
if (FW_WAKEUP_AFTER_RISC_ON(dev))
ret = s5p_mfc_wakeup_cmd(dev);
mfc_debug(2, "Ok, now will write a command to wakeup the system\n");
if (s5p_mfc_wait_for_done_dev(dev, S5P_FIMV_R2H_CMD_WAKEUP_RET)) {
mfc_err_dev("Failed to load firmware\n");
ret = -EIO;
goto err_mfc_wakeup;
}
dev->int_cond = 0;
if (dev->int_err != 0 || dev->int_type !=
S5P_FIMV_R2H_CMD_WAKEUP_RET) {
/* Failure. */
mfc_err_dev("Failed to wakeup - error: %d"
" int: %d.\n", dev->int_err, dev->int_type);
ret = -EIO;
goto err_mfc_wakeup;
}
err_mfc_wakeup:
s5p_mfc_clock_off(dev);
mfc_debug_leave();
return 0;
}
