int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < SAM3U_IRQ_EXTINT)
{
irq -= 4;
regaddr = NVIC_SYSH_PRIORITY(irq);
}
else
{
irq -= SAM3U_IRQ_EXTINT;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
sam3u_dumpnvic("prioritize", irq);
return OK;
}
int up_prioritize_irq(int irq, int priority)
{
uint32_t regaddr;
uint32_t regval;
int shift;
#ifdef CONFIG_ARMV7M_USEBASEPRI
DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS &&
priority >= NVIC_SYSH_DISABLE_PRIORITY &&
priority <= NVIC_SYSH_PRIORITY_MIN);
#else
DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
#endif
if (irq < SAM3U_IRQ_EXTINT)
{
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
* registers (0-3 are invalid)
*/
regaddr = NVIC_SYSH_PRIORITY(irq);
irq -= 4;
}
else
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
irq -= SAM3U_IRQ_EXTINT;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
regval = getreg32(regaddr);
shift = ((irq & 3) << 3);
regval &= ~(0xff << shift);
regval |= (priority << shift);
putreg32(regval, regaddr);
sam3u_dumpnvic("prioritize", irq);
return OK;
}
void up_enable_irq(int irq)
{
uint32_t regaddr;
uint32_t regval;
uint32_t bit;
if (sam3u_irqinfo(irq, ®addr, &bit) == 0)
{
/* Set the appropriate bit in the register to enable the interrupt */
regval = getreg32(regaddr);
regval |= bit;
putreg32(regval, regaddr);
}
#ifdef CONFIG_GPIO_IRQ
else
{
/* Maybe it is a (derived) GPIO IRQ */
sam3u_gpioirqenable(irq);
}
#endif
sam3u_dumpnvic("enable", irq);
}
void up_irqinitialize(void)
{
/* Disable all interrupts */
putreg32(0, NVIC_IRQ0_31_ENABLE);
/* Set up the vector table address.
*
* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
* vector table that requires special initialization.
*/
#if defined(CONFIG_ARCH_RAMVECTORS)
up_ramvec_initialize();
#elif defined(CONFIG_STM32_DFU)
putreg32((uint32_t)sam3u_vectors, NVIC_VECTAB);
#endif
/* Set all interrrupts (and exceptions) to the default priority */
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY);
putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY);
/* currents_regs is non-NULL only while processing an interrupt */
current_regs = NULL;
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
* exception is used for performing context switches; The Hard Fault
* must also be caught because a SVCall may show up as a Hard Fault
* under certain conditions.
*/
irq_attach(SAM3U_IRQ_SVCALL, up_svcall);
irq_attach(SAM3U_IRQ_HARDFAULT, up_hardfault);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(SAM3U_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
#ifdef CONFIG_ARMV7M_USEBASEPRI
sam3u_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
#endif
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
#ifdef CONFIG_ARMV7M_MPU
irq_attach(SAM3U_IRQ_MEMFAULT, up_memfault);
up_enable_irq(SAM3U_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG
irq_attach(SAM3U_IRQ_NMI, sam3u_nmi);
#ifndef CONFIG_ARMV7M_MPU
irq_attach(SAM3U_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(SAM3U_IRQ_BUSFAULT, sam3u_busfault);
irq_attach(SAM3U_IRQ_USAGEFAULT, sam3u_usagefault);
irq_attach(SAM3U_IRQ_PENDSV, sam3u_pendsv);
irq_attach(SAM3U_IRQ_DBGMONITOR, sam3u_dbgmonitor);
irq_attach(SAM3U_IRQ_RESERVED, sam3u_reserved);
#endif
sam3u_dumpnvic("initial", SAM3U_IRQ_NIRQS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*/
#ifdef CONFIG_GPIO_IRQ
sam3u_gpioirqinitialize();
#endif
/* And finally, enable interrupts */
irqenable();
#endif
}
