uint32_t power_read_reset_status(void)
{
struct exynos5_power *power =
samsung_get_base_power();
return power->inform1;
}
void power_enable_dp_phy(void)
{
struct exynos5_power *power =
samsung_get_base_power();
setbits_le32(&power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
}
static uint32_t exynos4_get_reset_status(void)
{
struct exynos4_power *power =
(struct exynos4_power *)samsung_get_base_power();
return power->inform1;
}
static void exynos4_power_exit_wakeup(void)
{
struct exynos4_power *power =
(struct exynos4_power *)samsung_get_base_power();
typedef void (*resume_func)(void);
((resume_func)power->inform0)();
}
void power_enable_hw_thermal_trip(void)
{
struct exynos5_power *power =
samsung_get_base_power();
/* Enable HW thermal trip */
setbits_le32(&power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
}
void power_disable_usb_phy(void)
{
struct exynos5_power *power =
samsung_get_base_power();
/* Disabling USBHost_PHY */
clrbits_le32(&power->usb_host_phy_ctrl, POWER_USB_HOST_PHY_CTRL_EN);
}
void ps_hold_setup(void)
{
struct exynos5_power *power =
samsung_get_base_power();
/* Set PS-Hold high */
setbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH);
}
static void exynos5_set_ps_hold_ctrl(void)
{
struct exynos5_power *power =
(struct exynos5_power *)samsung_get_base_power();
/* Set PS-Hold high */
setbits_le32(&power->ps_hold_control,
EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
}
static void trats_low_power_mode(void)
{
struct exynos4_clock *clk =
(struct exynos4_clock *)samsung_get_base_clock();
struct exynos4_power *pwr =
(struct exynos4_power *)samsung_get_base_power();
/* Power down CORE1 */
/* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */
writel(0x0, &pwr->arm_core1_configuration);
/* Change the APLL frequency */
/* ENABLE (1 enable) | LOCKED (1 locked) */
/* [31] | [29] */
/* FSEL | MDIV | PDIV | SDIV */
/* [27] | [25:16] | [13:8] | [2:0] */
writel(0xa0c80604, &clk->apll_con0);
/* Change CPU0 clock divider */
/* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */
/* [30:28] | [26:24] | [22:20] | [18:16] */
/* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */
/* [14:12] | [10:8] | [6:4] | [2:0] */
writel(0x00000100, &clk->div_cpu0);
/* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */
while (readl(&clk->div_stat_cpu0) & 0x1111111)
continue;
/* Change clock divider ratio for DMC */
/* DMCP_RATIO | DMCD_RATIO */
/* [22:20] | [18:16] */
/* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */
/* [14:12] | [10:8] | [6:4] | [2:0] */
writel(0x13113117, &clk->div_dmc0);
/* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */
while (readl(&clk->div_stat_dmc0) & 0x11111111)
continue;
/* Turn off unnecessary power domains */
writel(0x0, &pwr->xxti_configuration); /* XXTI */
writel(0x0, &pwr->cam_configuration); /* CAM */
writel(0x0, &pwr->tv_configuration); /* TV */
writel(0x0, &pwr->mfc_configuration); /* MFC */
writel(0x0, &pwr->g3d_configuration); /* G3D */
writel(0x0, &pwr->gps_configuration); /* GPS */
writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */
/* Turn off unnecessary clocks */
writel(0x0, &clk->gate_ip_cam); /* CAM */
writel(0x0, &clk->gate_ip_tv); /* TV */
writel(0x0, &clk->gate_ip_mfc); /* MFC */
writel(0x0, &clk->gate_ip_g3d); /* G3D */
writel(0x0, &clk->gate_ip_image); /* IMAGE */
writel(0x0, &clk->gate_ip_gps); /* GPS */
}
static void exynos5_set_xclkout(void)
{
struct exynos5_power *power =
(struct exynos5_power *)samsung_get_base_power();
/* use xxti for xclk out */
clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
PMU_DEBUG_XXTI);
}
/* This function never returns */
void power_shutdown(void)
{
struct exynos5_power *power =
samsung_get_base_power();
clrbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH);
hlt();
}
/* Enables hardware tripping to power off the system when TMU fails */
void set_hw_thermal_trip(void)
{
if (cpu_is_exynos5()) {
struct exynos5_power *power =
(struct exynos5_power *)samsung_get_base_power();
/* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
}
}
void power_reset(void)
{
struct exynos5_power *power =
samsung_get_base_power();
/* Clear inform1 so there's no change we think we've got a wake reset */
power->inform1 = 0;
setbits_le32(&power->sw_reset, 1);
}
static void exynos5_dp_phy_control(unsigned int enable)
{
unsigned int cfg;
struct exynos5_power *power =
(struct exynos5_power *)samsung_get_base_power();
cfg = readl(&power->dptx_phy_control);
if (enable)
cfg |= EXYNOS_DP_PHY_ENABLE;
else
cfg &= ~EXYNOS_DP_PHY_ENABLE;
writel(cfg, &power->dptx_phy_control);
}
static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
{
struct exynos5_power *power =
(struct exynos5_power *)samsung_get_base_power();
if (enable) {
/* Enabling USBDRD_PHY */
setbits_le32(&power->usbdrd_phy_control,
POWER_USB_DRD_PHY_CTRL_EN);
} else {
/* Disabling USBDRD_PHY */
clrbits_le32(&power->usbdrd_phy_control,
POWER_USB_DRD_PHY_CTRL_EN);
}
}
int board_mmc_init(bd_t *bis)
{
int err;
struct exynos4_power *power = (struct exynos4_power *)samsung_get_base_power();
if ((power->om_stat & 0x1E) == 0x8) {
err = board_emmc_init();
err = board_sdmmc_init();
} else {
err = board_sdmmc_init();
err = board_emmc_init();
}
return 0;
}
int exynos_init(void)
{
struct exynos4_power *pwr =
(struct exynos4_power *)samsung_get_base_power();
check_hw_revision();
printf("HW Revision:\t0x%04x\n", board_rev);
/*
* First bootloader on the TRATS2 platform uses
* INFORM4 and INFORM5 registers for recovery
*
* To indicate correct boot chain - those two
* registers must be cleared out
*/
writel(0, &pwr->inform4);
writel(0, &pwr->inform5);
return 0;
}
void power_enable_usb_phy(void)
{
struct exynos5_sysreg *sysreg =
samsung_get_base_sysreg();
struct exynos5_power *power =
samsung_get_base_power();
unsigned int phy_cfg;
/* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
phy_cfg = readl(&sysreg->usb20_phy_cfg);
if (phy_cfg & USB20_PHY_CFG_EN) {
printk(BIOS_DEBUG, "USB 2.0 HOST link already selected\n");
} else {
phy_cfg |= USB20_PHY_CFG_EN;
writel(phy_cfg, &sysreg->usb20_phy_cfg);
}
/* Enabling USBHOST_PHY */
setbits_le32(&power->usb_host_phy_ctrl, POWER_USB_HOST_PHY_CTRL_EN);
}
static void exynos4_mipi_phy_control(unsigned int dev_index,
unsigned int enable)
{
struct exynos4_power *pmu =
(struct exynos4_power *)samsung_get_base_power();
unsigned int addr, cfg = 0;
if (dev_index == 0)
addr = (unsigned int)&pmu->mipi_phy0_control;
else
addr = (unsigned int)&pmu->mipi_phy1_control;
cfg = readl(addr);
if (enable)
cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
else
cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
writel(cfg, addr);
}
static void board_power_init(void)
{
struct exynos4_power *pwr =
(struct exynos4_power *)samsung_get_base_power();
/* PS HOLD */
writel(EXYNOS4_PS_HOLD_CON_VAL, (unsigned int)&pwr->ps_hold_control);
/* Set power down */
writel(0, (unsigned int)&pwr->cam_configuration);
writel(0, (unsigned int)&pwr->tv_configuration);
writel(0, (unsigned int)&pwr->mfc_configuration);
writel(0, (unsigned int)&pwr->g3d_configuration);
writel(0, (unsigned int)&pwr->lcd1_configuration);
writel(0, (unsigned int)&pwr->gps_configuration);
writel(0, (unsigned int)&pwr->gps_alive_configuration);
/* It is necessary to power down core 1 */
/* to successfully boot CPU1 in kernel */
writel(0, (unsigned int)&pwr->arm_core1_configuration);
}
void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
{
struct exynos4412_power *power =
(struct exynos4412_power *)samsung_get_base_power();
if (enable) {
/* Enabling USBHOST_PHY */
setbits_le32(&power->usbhost_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
setbits_le32(&power->hsic1_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
setbits_le32(&power->hsic2_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
} else {
/* Disabling USBHOST_PHY */
clrbits_le32(&power->usbhost_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
clrbits_le32(&power->hsic1_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
clrbits_le32(&power->hsic2_phy_control,
POWER_USB_HOST_PHY_CTRL_EN);
}
}
int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
{
struct exynos5420_clock *clk =
(struct exynos5420_clock *)samsung_get_base_clock();
struct exynos5420_power *power =
(struct exynos5420_power *)samsung_get_base_power();
struct exynos5420_phy_control *phy0_ctrl, *phy1_ctrl;
struct exynos5420_dmc *drex0, *drex1;
struct exynos5420_tzasc *tzasc0, *tzasc1;
struct exynos5_power *pmu;
uint32_t val, n_lock_r, n_lock_w_phy0, n_lock_w_phy1;
uint32_t lock0_info, lock1_info;
int chip;
int i;
phy0_ctrl = (struct exynos5420_phy_control *)samsung_get_base_dmc_phy();
phy1_ctrl = (struct exynos5420_phy_control *)(samsung_get_base_dmc_phy()
+ DMC_OFFSET);
drex0 = (struct exynos5420_dmc *)samsung_get_base_dmc_ctrl();
drex1 = (struct exynos5420_dmc *)(samsung_get_base_dmc_ctrl()
+ DMC_OFFSET);
tzasc0 = (struct exynos5420_tzasc *)samsung_get_base_dmc_tzasc();
tzasc1 = (struct exynos5420_tzasc *)(samsung_get_base_dmc_tzasc()
+ DMC_OFFSET);
pmu = (struct exynos5_power *)EXYNOS5420_POWER_BASE;
if (CONFIG_NR_DRAM_BANKS > 4) {
/* Need both controllers. */
mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_2;
mem->chips_per_channel = 2;
mem->chips_to_configure = 2;
} else {
/* 2GB requires a single controller */
mem->memcontrol |= DMC_MEMCONTROL_NUM_CHIP_1;
}
/* Enable PAUSE for DREX */
setbits_le32(&clk->pause, ENABLE_BIT);
/* Enable BYPASS mode */
setbits_le32(&clk->bpll_con1, BYPASS_EN);
writel(MUX_BPLL_SEL_FOUTBPLL, &clk->src_cdrex);
do {
val = readl(&clk->mux_stat_cdrex);
val &= BPLL_SEL_MASK;
} while (val != FOUTBPLL);
clrbits_le32(&clk->bpll_con1, BYPASS_EN);
/* Specify the DDR memory type as DDR3 */
val = readl(&phy0_ctrl->phy_con0);
val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
writel(val, &phy0_ctrl->phy_con0);
val = readl(&phy1_ctrl->phy_con0);
val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
val |= (DDR_MODE_DDR3 << PHY_CON0_CTRL_DDR_MODE_SHIFT);
writel(val, &phy1_ctrl->phy_con0);
/* Set Read Latency and Burst Length for PHY0 and PHY1 */
val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
writel(val, &phy0_ctrl->phy_con42);
writel(val, &phy1_ctrl->phy_con42);
val = readl(&phy0_ctrl->phy_con26);
val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
writel(val, &phy0_ctrl->phy_con26);
val = readl(&phy1_ctrl->phy_con26);
val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
writel(val, &phy1_ctrl->phy_con26);
/*
* Set Driver strength for CK, CKE, CS & CA to 0x7
* Set Driver strength for Data Slice 0~3 to 0x7
*/
val = (0x7 << CA_CK_DRVR_DS_OFFSET) | (0x7 << CA_CKE_DRVR_DS_OFFSET) |
(0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
(0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
writel(val, &phy0_ctrl->phy_con39);
writel(val, &phy1_ctrl->phy_con39);
/* ZQ Calibration */
if (dmc_config_zq(mem, &phy0_ctrl->phy_con16, &phy1_ctrl->phy_con16,
&phy0_ctrl->phy_con17, &phy1_ctrl->phy_con17))
return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
/* DQ Signal */
val = readl(&phy0_ctrl->phy_con14);
val |= mem->phy0_pulld_dqs;
writel(val, &phy0_ctrl->phy_con14);
val = readl(&phy1_ctrl->phy_con14);
val |= mem->phy1_pulld_dqs;
writel(val, &phy1_ctrl->phy_con14);
val = MEM_TERM_EN | PHY_TERM_EN;
writel(val, &drex0->phycontrol0);
writel(val, &drex1->phycontrol0);
writel(mem->concontrol |
(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
&drex0->concontrol);
writel(mem->concontrol |
(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
&drex1->concontrol);
do {
val = readl(&drex0->phystatus);
} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
do {
val = readl(&drex1->phystatus);
} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
clrbits_le32(&drex0->concontrol, DFI_INIT_START);
clrbits_le32(&drex1->concontrol, DFI_INIT_START);
update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
/*
* Set Base Address:
* 0x2000_0000 ~ 0x5FFF_FFFF
* 0x6000_0000 ~ 0x9FFF_FFFF
*/
/* MEMBASECONFIG0 */
val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_0) |
DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
writel(val, &tzasc0->membaseconfig0);
writel(val, &tzasc1->membaseconfig0);
/* MEMBASECONFIG1 */
val = DMC_MEMBASECONFIGX_CHIP_BASE(DMC_CHIP_BASE_1) |
DMC_MEMBASECONFIGX_CHIP_MASK(DMC_CHIP_MASK);
writel(val, &tzasc0->membaseconfig1);
writel(val, &tzasc1->membaseconfig1);
/*
* Memory Channel Inteleaving Size
* Ares Channel interleaving = 128 bytes
*/
/* MEMCONFIG0/1 */
writel(mem->memconfig, &tzasc0->memconfig0);
writel(mem->memconfig, &tzasc1->memconfig0);
writel(mem->memconfig, &tzasc0->memconfig1);
writel(mem->memconfig, &tzasc1->memconfig1);
/* Precharge Configuration */
writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
&drex0->prechconfig0);
writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
&drex1->prechconfig0);
/*
* TimingRow, TimingData, TimingPower and Timingaref
* values as per Memory AC parameters
*/
writel(mem->timing_ref, &drex0->timingref);
writel(mem->timing_ref, &drex1->timingref);
writel(mem->timing_row, &drex0->timingrow0);
writel(mem->timing_row, &drex1->timingrow0);
writel(mem->timing_data, &drex0->timingdata0);
writel(mem->timing_data, &drex1->timingdata0);
writel(mem->timing_power, &drex0->timingpower0);
writel(mem->timing_power, &drex1->timingpower0);
if (reset) {
/*
* Send NOP, MRS and ZQINIT commands
* Sending MRS command will reset the DRAM. We should not be
* reseting the DRAM after resume, this will lead to memory
* corruption as DRAM content is lost after DRAM reset
*/
dmc_config_mrs(mem, &drex0->directcmd);
dmc_config_mrs(mem, &drex1->directcmd);
}
/*
* Get PHY_CON13 from both phys. Gate CLKM around reading since
* PHY_CON13 is glitchy when CLKM is running. We're paranoid and
* wait until we get a "fine lock", though a coarse lock is probably
* OK (we only use the coarse numbers below). We try to gate the
* clock for as short a time as possible in case SDRAM is somehow
* sensitive. sdelay(10) in the loop is arbitrary to make sure
* there is some time for PHY_CON13 to get updated. In practice
* no delay appears to be needed.
*/
val = readl(&clk->gate_bus_cdrex);
while (true) {
writel(val & ~0x1, &clk->gate_bus_cdrex);
lock0_info = readl(&phy0_ctrl->phy_con13);
writel(val, &clk->gate_bus_cdrex);
if ((lock0_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
break;
sdelay(10);
}
while (true) {
writel(val & ~0x2, &clk->gate_bus_cdrex);
lock1_info = readl(&phy1_ctrl->phy_con13);
writel(val, &clk->gate_bus_cdrex);
if ((lock1_info & CTRL_FINE_LOCKED) == CTRL_FINE_LOCKED)
break;
sdelay(10);
}
if (!reset) {
/*
* During Suspend-Resume & S/W-Reset, as soon as PMU releases
* pad retention, CKE goes high. This causes memory contents
* not to be retained during DRAM initialization. Therfore,
* there is a new control register(0x100431e8[28]) which lets us
* release pad retention and retain the memory content until the
* initialization is complete.
*/
writel(PAD_RETENTION_DRAM_COREBLK_VAL,
&power->pad_retention_dram_coreblk_option);
do {
val = readl(&power->pad_retention_dram_status);
} while (val != 0x1);
/*
* CKE PAD retention disables DRAM self-refresh mode.
* Send auto refresh command for DRAM refresh.
*/
for (i = 0; i < 128; i++) {
for (chip = 0; chip < mem->chips_to_configure; chip++) {
writel(DIRECT_CMD_REFA |
(chip << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(DIRECT_CMD_REFA |
(chip << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
}
}
}
if (mem->gate_leveling_enable) {
writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
val = PHY_CON2_RESET_VAL;
val |= INIT_DESKEW_EN;
writel(val, &phy0_ctrl->phy_con2);
writel(val, &phy1_ctrl->phy_con2);
val = readl(&phy0_ctrl->phy_con1);
val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
writel(val, &phy0_ctrl->phy_con1);
val = readl(&phy1_ctrl->phy_con1);
val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
writel(val, &phy1_ctrl->phy_con1);
n_lock_w_phy0 = (lock0_info & CTRL_LOCK_COARSE_MASK) >> 2;
n_lock_r = readl(&phy0_ctrl->phy_con12);
n_lock_r &= ~CTRL_DLL_ON;
n_lock_r |= n_lock_w_phy0;
writel(n_lock_r, &phy0_ctrl->phy_con12);
n_lock_w_phy1 = (lock1_info & CTRL_LOCK_COARSE_MASK) >> 2;
n_lock_r = readl(&phy1_ctrl->phy_con12);
n_lock_r &= ~CTRL_DLL_ON;
n_lock_r |= n_lock_w_phy1;
writel(n_lock_r, &phy1_ctrl->phy_con12);
val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
for (chip = 0; chip < mem->chips_to_configure; chip++) {
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
}
setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
val = readl(&phy0_ctrl->phy_con1);
val &= ~(CTRL_GATEDURADJ_MASK);
writel(val, &phy0_ctrl->phy_con1);
val = readl(&phy1_ctrl->phy_con1);
val &= ~(CTRL_GATEDURADJ_MASK);
writel(val, &phy1_ctrl->phy_con1);
writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
i = TIMEOUT_US;
while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
RDLVL_COMPLETE_CHO) && (i > 0)) {
/*
* TODO(waihong): Comment on how long this take to
* timeout
*/
sdelay(100);
i--;
}
if (!i)
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
i = TIMEOUT_US;
while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
RDLVL_COMPLETE_CHO) && (i > 0)) {
/*
* TODO(waihong): Comment on how long this take to
* timeout
*/
sdelay(100);
i--;
}
if (!i)
return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
writel(0, &phy0_ctrl->phy_con14);
writel(0, &phy1_ctrl->phy_con14);
val = (0x3 << DIRECT_CMD_BANK_SHIFT);
for (chip = 0; chip < mem->chips_to_configure; chip++) {
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex0->directcmd);
writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
&drex1->directcmd);
}
/* Common Settings for Leveling */
val = PHY_CON12_RESET_VAL;
writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);
writel((val + n_lock_w_phy1), &phy1_ctrl->phy_con12);
setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
}
unsigned int get_boot_mode(void)
{
unsigned int om_pin = samsung_get_base_power();
return readl(om_pin) & OM_PIN_MASK;
}
