static void exynos5_pm_prepare(void)
{
unsigned int tmp;
if (exynos5_sleep_gpio_table_set)
exynos5_sleep_gpio_table_set();
if (samsung_rev() < EXYNOS5250_REV_1_0) {
/* Disable USE_RETENTION of JPEG_MEM_OPTION */
tmp = __raw_readl(EXYNOS5_JPEG_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
__raw_writel(tmp, EXYNOS5_JPEG_MEM_OPTION);
}
if (samsung_rev() >= EXYNOS5250_REV_1_0) {
tmp = __raw_readl(EXYNOS5_ARM_L2_OPTION);
tmp &= ~(1 << 4);
__raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
}
/* Set value of power down register for sleep mode */
exynos5_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, REG_INFORM1);
/* ensure at least INFORM0 has the resume address */
__raw_writel(virt_to_phys(s3c_cpu_resume), REG_INFORM0);
if (exynos4_is_c2c_use()) {
tmp = __raw_readl(EXYNOS5_INTRAM_MEM_OPTION);
tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
__raw_writel(tmp, EXYNOS5_INTRAM_MEM_OPTION);
}
s3c_pm_do_restore_core(exynos5_set_clksrc, ARRAY_SIZE(exynos5_set_clksrc));
}
static void exynos5250_target_for_mif(struct busfreq_data *data, int div_index)
{
unsigned int tmp;
/* Change Divider - CDREX */
tmp = data->cdrex_divtable[div_index];
__raw_writel(tmp, EXYNOS5_CLKDIV_CDREX);
if (samsung_rev() < EXYNOS5250_REV_1_0) {
do {
tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_CDREX);
} while (tmp & 0x11111111);
} else {
do {
tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_CDREX);
} while (tmp & 0x11110011); \
}
if (samsung_rev() < EXYNOS5250_REV_1_0) {
tmp = data->cdrex2_divtable[div_index];
__raw_writel(tmp, EXYNOS5_CLKDIV_CDREX2);
do {
tmp = __raw_readl(EXYNOS5_CLKDIV_STAT_CDREX2);
} while (tmp & 0x1);
}
}
static mali_bool mali_dvfs_table_update(void)
{
unsigned int i;
unsigned int step_num = MALI_DVFS_STEPS;
if(samsung_rev() < EXYNOS4412_REV_2_0)
step_num = MALI_DVFS_STEPS - 1;
if(soc_is_exynos4412()) {
if (exynos_armclk_max == 1000000) {
MALI_PRINT(("::C::exynos_result_of_asv : %d\n", exynos_result_of_asv));
for (i = 0; i < step_num; i++) {
mali_dvfs[i].vol = asv_3d_volt_9_table_1ghz_type[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d \n", i, mali_dvfs[i].vol));
}
} else if(((is_special_flag() >> G3D_LOCK_FLAG) & 0x1) && (samsung_rev() >= EXYNOS4412_REV_2_0)) {
MALI_PRINT(("::L::exynos_result_of_asv : %d\n", exynos_result_of_asv));
for (i = 0; i < step_num; i++) {
mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv] + 25000;
MALI_PRINT(("mali_dvfs[%d].vol = %d \n ", i, mali_dvfs[i].vol));
}
} else if (samsung_rev() >= EXYNOS4412_REV_2_0) {
MALI_PRINT(("::P::exynos_result_of_asv : %d\n", exynos_result_of_asv));
for (i = 0; i < step_num; i++) {
mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d \n", i, mali_dvfs[i].vol));
}
} else {
MALI_PRINT(("::Q::exynos_result_of_asv : %d\n", exynos_result_of_asv));
for (i = 0; i < step_num; i++) {
mali_dvfs[i].vol = asv_3d_volt_9_table[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d \n", i, mali_dvfs[i].vol));
}
}
}
void exynos4_c2c_request_pwr_mode(enum c2c_pwr_mode mode)
{
if (soc_is_exynos4412() && (samsung_rev() < EXYNOS4412_REV_1_0))
exynos4_config_for_c2c[0].val = 0x3;
else
exynos4_config_for_c2c[0].val = 0x0;
switch (mode) {
/* If C2C mode is MAXIMAL LATENCY */
case MAX_LATENCY:
exynos4_config_for_c2c[1].val = 0x0;
if (soc_is_exynos4412() && (samsung_rev() < EXYNOS4412_REV_1_0))
exynos4_config_for_c2c[2].val = 0x1;
else
exynos4_config_for_c2c[2].val = 0x0;
#ifdef CONFIG_EXYNOS_C2C
exynos4_config_for_c2c[3].val = 0x0;
#endif
break;
/* If C2C mode is Minimal or Short LATENCY */
default:
exynos4_config_for_c2c[1].val = 0x3;
exynos4_config_for_c2c[2].val = 0x1;
#ifdef CONFIG_EXYNOS_C2C
exynos4_config_for_c2c[3].val = 0x1;
#endif
break;
}
}
void exynos4_setup_mshci_cfg_ddr(struct platform_device *dev, int ddr)
{
if (ddr) {
#ifdef CONFIG_EXYNOS4_MSHC_EPLL_45MHZ
__raw_writel(0x00, DIV_FSYS3);
#elif defined(CONFIG_EXYNOS4_MSHC_VPLL_46MHZ)
__raw_writel(0x01, DIV_FSYS3);
#else
if ((soc_is_exynos4412() || soc_is_exynos4212()) &&
samsung_rev() >= EXYNOS4412_REV_1_0) {
__raw_writel(0x1, DIV_FSYS3);
} else
__raw_writel(0x05, DIV_FSYS3);
#endif
} else {
#ifdef CONFIG_EXYNOS4_MSHC_EPLL_45MHZ
__raw_writel(0x01, DIV_FSYS3);
#elif defined(CONFIG_EXYNOS4_MSHC_VPLL_46MHZ)
__raw_writel(0x03, DIV_FSYS3);
#else
if ((soc_is_exynos4412() || soc_is_exynos4212()) &&
samsung_rev() >= EXYNOS4412_REV_1_0)
__raw_writel(0x3, DIV_FSYS3);
else
__raw_writel(0xb, DIV_FSYS3);
#endif
}
}
void exynos5_cpu_suspend(void)
{
unsigned int tmp;
/* Disable wakeup by EXT_GIC */
tmp = __raw_readl(EXYNOS5_WAKEUP_MASK);
tmp |= EXYNOS5_DEFAULT_WAKEUP_MACK;
__raw_writel(tmp, EXYNOS5_WAKEUP_MASK);
/*
* GPS LPI mask.
*/
if (samsung_rev() < EXYNOS5250_REV_1_0)
__raw_writel(0x10000, EXYNOS5_GPS_LPI);
if (samsung_rev() >= EXYNOS5250_REV_1_0)
exynos4_reset_assert_ctrl(0);
#ifdef CONFIG_ARM_TRUSTZONE
exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
#else
/* issue the standby signal into the pm unit. */
cpu_do_idle();
#endif
}
static mali_bool mali_pegasus_dvfs_table_update(void)
{
unsigned int i;
unsigned int step_num = MALI_DVFS_STEPS;
if(samsung_rev() < EXYNOS4412_REV_2_0)
step_num = MALI_DVFS_STEPS-1;
if(soc_is_exynos4412()) {
/*check it's pega-prime or pega-Q*/
if(samsung_rev() < EXYNOS4412_REV_2_0) {
step_num = MALI_DVFS_STEPS-1;
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_4412_9_table[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
}
}
/* For Pega-Prime e-fuse, add 25mV from default ASV table*/
else if((is_special_flag() >> G3D_LOCK_FLAG) & 0x1) {
for (i = 0; i < step_num; i++) {
MALI_PRINT(("Pega-Prime e-fuse(add 25mV):::result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv] + 25000;
MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
}
}
/* pega-prime default ASV table */
else {
for (i = 0; i < step_num; i++) {
MALI_PRINT(("pega-prime default ASV table:::result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
}
}
}
int mfc_power_off(void)
{
#ifdef CONFIG_PM_RUNTIME
if ((soc_is_exynos4212() && (samsung_rev() < EXYNOS4212_REV_1_0)) ||
(soc_is_exynos4412() && (samsung_rev() < EXYNOS4412_REV_1_1)))
return 0;
else
return pm_runtime_put_sync(pm->device);
#else
atomic_set(&pm->power, 0);
return 0;
#endif
}
int fimc_clk_rate(void)
{
if (samsung_rev() >= EXYNOS4412_REV_2_0)
return 180000000;
else
return 166750000;
}
void exynos5_sys_powerdown_conf(enum sys_powerdown mode)
{
unsigned int count = entry_cnt;
unsigned int i;
exynos5_init_pmu();
for (; count > 0; count--)
__raw_writel(exynos5_pmu_config[count - 1].val[mode],
exynos5_pmu_config[count - 1].reg);
if (samsung_rev() < EXYNOS5250_REV_1_0) {
for (i = 0; i < ARRAY_SIZE(exynos52xx_pmu_config_gps); i++) {
__raw_writel(exynos52xx_pmu_config_gps[i].val[mode],
exynos52xx_pmu_config_gps[i].reg);
}
}
if ((mode != SYS_AFTR) && (exynos4_is_c2c_use())) {
pr_info("%s power mode enter with C2C Enabling\n"
, (mode == SYS_LPA) ? "LPA" : "SLEEP");
for (i = 0; i < ARRAY_SIZE(exynos52xx_pmu_c2c_config); i++) {
__raw_writel(exynos52xx_pmu_c2c_config[i].val[mode],
exynos52xx_pmu_c2c_config[i].reg);
}
}
}
int exynos4_pmu_cp_init(void)
{
u32 cp_ctrl;
int ret = 0;
unsigned int gpio;
pr_info("%s\n", __func__);
if (samsung_rev() == EXYNOS3470_REV_2_0) {
gpio = EXYNOS4_GPM2(3);
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(1));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
s5p_gpio_set_pd_cfg(gpio, S5P_GPIO_PD_OUTPUT1);
s5p_gpio_set_data(gpio, 1);
s5p_gpio_set_pd_pull(gpio, S3C_GPIO_PULL_NONE);
}
cp_ctrl = __raw_readl(EXYNOS3470_CP_CTRL);
cp_ctrl |= MASK_CP_PWRDN_DONE;
__raw_writel(cp_ctrl, EXYNOS3470_CP_CTRL);
#ifdef DEBUG_SLEEP_WITHOUT_CP
/* test purpose */
exynos4_set_cp_power_onoff(CP_POWER_ON);
exynos4_cp_reset();
exynos4_clear_cp_reset_req();
exynos4_set_cp_power_onoff(CP_POWER_OFF);
exynos4_set_cp_power_onoff(CP_POWER_ON);
#endif
return ret;
}
int mali_dvfs_bottom_lock_push(int lock_step)
{
int prev_status = _mali_osk_atomic_read(&bottomlock_status);
if (prev_status < 0) {
MALI_PRINT(("gpu bottom lock status is not valid for push\n"));
return -1;
}
// not a bad idea to limit locking to 4th step, so let's leave this -gm
if (samsung_rev() < EXYNOS4412_REV_2_0)
lock_step = min(lock_step, MALI_DVFS_STEPS - 2);
else
lock_step = min(lock_step, MALI_DVFS_STEPS - 1);
if (bottom_lock_step < lock_step) {
bottom_lock_step = lock_step;
if (get_mali_dvfs_status() < lock_step) {
mali_regulator_set_voltage(mali_dvfs[lock_step].vol,
mali_dvfs[lock_step].vol);
mali_clk_set_rate(mali_dvfs[lock_step].clock,
mali_dvfs[lock_step].freq);
set_mali_dvfs_current_step(lock_step);
}
}
return _mali_osk_atomic_inc_return(&bottomlock_status);
}
static mali_bool mali_dvfs_table_update(void)
{
unsigned int i;
unsigned int step_num = MALI_DVFS_STEPS;
if(soc_is_exynos4412()) {
if (exynos_armclk_max == 1000000) {
step_num = MALI_DVFS_STEPS - 1;
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table_1ghz_type[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d 1ghz_type\n", i, mali_dvfs[i].vol));
}
} else if (samsung_rev() >= EXYNOS4412_REV_2_0) {
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d 1.6ghz_type\n", i, mali_dvfs[i].vol));
}
} else {
step_num = MALI_DVFS_STEPS - 1;
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d 1.4ghz_type\n", i, mali_dvfs[i].vol));
}
}
}
return MALI_TRUE;
}
/*
* Enable the SCU
*/
void scu_enable(void __iomem *scu_base)
{
u32 scu_ctrl;
#ifdef CONFIG_ARM_ERRATA_764369
/* Cortex-A9 only */
if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
scu_ctrl = __raw_readl(scu_base + 0x30);
if (!(scu_ctrl & 1))
__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
}
#endif
scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
/* already enabled? */
if (scu_ctrl & 1)
return;
if ((soc_is_exynos4412() && (samsung_rev() >= EXYNOS4412_REV_1_0)) ||
soc_is_exynos4210())
scu_ctrl |= (1<<3);
scu_ctrl |= 1;
__raw_writel(scu_ctrl, scu_base + SCU_CTRL);
/*
* Ensure that the data accessed by CPU0 before the SCU was
* initialised is visible to the other CPUs.
*/
flush_cache_all();
#ifdef CONFIG_MACH_PX
logbuf_force_unlock();
#endif
}
void __init exynos5_odroidxu_mmc_init(void)
{
int OM_STAT=0;
if (samsung_rev() < EXYNOS5410_REV_1_0)
smdk5410_dwmci0_pdata.caps &=
~(MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR);
#ifndef CONFIG_EXYNOS_EMMC_HS200
smdk5410_dwmci0_pdata.caps2 &=
~MMC_CAP2_HS200_1_8V_SDR;
#endif
exynos_dwmci_set_platdata(&smdk5410_dwmci0_pdata, 0);
exynos_dwmci_set_platdata(&smdk5410_dwmci2_pdata, 2);
OM_STAT = readl(EXYNOS_OM_STAT);
if(OM_STAT == 0x4) { // T-Flash_CH2
exynos_dwmci_set_platdata(&smdk5410_dwmci2_pdata, 2);
exynos_dwmci_set_platdata(&smdk5410_dwmci0_pdata, 0);
platform_add_devices(odroidxu_tflash_devices, ARRAY_SIZE(odroidxu_tflash_devices));
}
else { // emmc44_CH0
exynos_dwmci_set_platdata(&smdk5410_dwmci0_pdata, 0);
exynos_dwmci_set_platdata(&smdk5410_dwmci2_pdata, 2);
platform_add_devices(odroidxu_emmc_devices, ARRAY_SIZE(odroidxu_emmc_devices));
}
}
static int exynos_dwmci2_get_bus_wd(u32 slot_id)
{
if (samsung_rev() < EXYNOS5410_REV_1_0)
return 1;
else
return 4;
}
void __init exynos4_map_io(void)
{
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_0)
iotable_init(exynos4_iodesc0, ARRAY_SIZE(exynos4_iodesc0));
else
iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
/* initialize device information early */
exynos4_default_sdhci0();
exynos4_default_sdhci1();
exynos4_default_sdhci2();
exynos4_default_sdhci3();
s3c_adc_setname("samsung-adc-v3");
s3c_fimc_setname(0, "exynos4-fimc");
s3c_fimc_setname(1, "exynos4-fimc");
s3c_fimc_setname(2, "exynos4-fimc");
s3c_fimc_setname(3, "exynos4-fimc");
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_i2c2_setname("s3c2440-i2c");
s5p_fb_setname(0, "exynos4-fb");
s5p_hdmi_setname("exynos4-hdmi");
}
static int __init exynos4_l2x0_cache_init(void)
{
u32 tag_latency = 0x110;
u32 data_latency = soc_is_exynos4210() ? 0x110 : 0x120;
u32 prefetch = (soc_is_exynos4412() &&
samsung_rev() >= EXYNOS4412_REV_1_0) ?
0x71000007 : 0x30000007;
u32 aux_val = 0x7C470001;
u32 aux_mask = 0xC200FFFF;
#ifdef CONFIG_ARM_TRUSTZONE
exynos_smc(SMC_CMD_L2X0SETUP1, tag_latency, data_latency, prefetch);
exynos_smc(SMC_CMD_L2X0SETUP2,
L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
aux_val, aux_mask);
exynos_smc(SMC_CMD_L2X0INVALL, 0, 0, 0);
exynos_smc(SMC_CMD_L2X0CTRL, 1, 0, 0);
#else
__raw_writel(tag_latency, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
__raw_writel(data_latency, S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL);
__raw_writel(prefetch, S5P_VA_L2CC + L2X0_PREFETCH_CTRL);
__raw_writel(L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN,
S5P_VA_L2CC + L2X0_POWER_CTRL);
#endif
l2x0_init(S5P_VA_L2CC, aux_val, aux_mask);
#ifdef CONFIG_ARM_TRUSTZONE
#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
outer_cache.set_debug = exynos4_l2x0_set_debug;
#endif
#endif
return 0;
}
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup)
{
u32 validatedStep=step;
int err;
if (mali_step_lock > -1 && step != mali_step_lock) {
step = mali_step_lock;
}
#ifdef CONFIG_REGULATOR
if (mali_regulator_get_usecount() == 0) {
MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n"));
return MALI_FALSE;
}
#endif
if (boostup) {
#ifdef CONFIG_REGULATOR
/*change the voltage*/
mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
/*change the clock*/
mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
} else {
/*change the clock*/
mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
#ifdef CONFIG_REGULATOR
/*change the voltage*/
mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
}
#ifdef EXYNOS4_ASV_ENABLED
#ifndef CONFIG_ABB_CONTROL
if (samsung_rev() < EXYNOS4412_REV_2_0) {
if (mali_dvfs[step].clock == 160)
exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V);
else
exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V);
}
#else
abb_target(ABB_G3D, mali_dvfs[step].clock*1000);
#endif
#endif
set_mali_dvfs_current_step(validatedStep);
/*for future use*/
maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep];
#if CPUFREQ_LOCK_DURING_440
/* lock/unlock CPU freq by Mali */
if (mali_dvfs[step].clock == 440)
err = cpufreq_lock_by_mali(1200);
else
cpufreq_unlock_by_mali();
#endif
return MALI_TRUE;
}
void __init exynos4_init_irq(void)
{
int irq;
gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
gic_init(0, IRQ_PPI_MCT_L, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
gic_arch_extn.irq_set_wake = s3c_irq_wake;
for (irq = 0; irq < COMMON_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, COMBINER_MAP(irq));
}
if (soc_is_exynos4412() && (samsung_rev() >= EXYNOS4412_REV_1_0)) {
for (irq = COMMON_COMBINER_NR; irq < MAX_COMBINER_NR; irq++) {
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, COMBINER_MAP(irq));
}
}
/* The parameters of s5p_init_irq() are for VIC init.
* Theses parameters should be NULL and 0 because EXYNOS4
* uses GIC instead of VIC.
*/
s5p_init_irq(NULL, 0);
}
void change_all_power_base_to(unsigned int cluster)
{
int i;
int offset = 0;
if (!soc_is_exynos5410() && !soc_is_exynos5420())
return;
if (soc_is_exynos5410()) {
if (samsung_rev() < EXYNOS5410_REV_1_0) {
if (cluster == 0)
offset = 4;
} else {
if (cluster != 0)
offset = 4;
}
} else {
if (cluster)
offset = 4;
}
for (i = 0; i < 4; i++) {
cpu_boot_info[i].power_base =
EXYNOS_ARM_CORE_CONFIGURATION(offset + i);
}
}
static void exynos5_init_pmu(void)
{
unsigned int i;
unsigned int tmp;
/*
* Enable both SC_FEEDBACK and SC_COUNTER
*/
for (i = 0 ; i < ARRAY_SIZE(list_both_cnt_feed) ; i++) {
tmp = __raw_readl(list_both_cnt_feed[i]);
tmp |= (EXYNOS5_USE_SC_FEEDBACK |
EXYNOS5_USE_SC_COUNTER);
__raw_writel(tmp, list_both_cnt_feed[i]);
}
if (samsung_rev() < EXYNOS5250_REV_1_0) {
tmp = __raw_readl(EXYNOS5_GPS_OPTION);
tmp |= (EXYNOS5_USE_SC_FEEDBACK |
EXYNOS5_USE_SC_COUNTER);
__raw_writel(tmp, EXYNOS5_GPS_OPTION);
}
/*
* SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable
* MANUAL_L2RSTDISABLE_CONTROL_BITFIELD Enable
*/
if (samsung_rev() < EXYNOS5250_REV_1_0) {
tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
tmp |= (EXYNOS5_MANUAL_L2RSTDISABLE_CONTROL |
EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN);
__raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
} else {
tmp = __raw_readl(EXYNOS5_ARM_COMMON_OPTION);
tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
__raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION);
}
/*
* Disable WFI/WFE on XXX_OPTION
*/
for (i = 0 ; i < ARRAY_SIZE(list_diable_wfi_wfe) ; i++) {
tmp = __raw_readl(list_diable_wfi_wfe[i]);
tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE |
EXYNOS5_OPTION_USE_STANDBYWFI);
__raw_writel(tmp, list_diable_wfi_wfe[i]);
}
}
/*
* exynos4_map_io
*
* register the standard cpu IO areas
*/
void __init exynos4_map_io(void)
{
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
if (soc_is_exynos4210()) {
iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
if (samsung_rev() == EXYNOS4210_REV_0)
iotable_init(exynos4210_iodesc_rev_0,
ARRAY_SIZE(exynos4210_iodesc_rev_0));
else
iotable_init(exynos4210_iodesc_rev_1,
ARRAY_SIZE(exynos4210_iodesc_rev_1));
} else {
iotable_init(exynos4212_iodesc, ARRAY_SIZE(exynos4212_iodesc));
}
#ifdef CONFIG_S3C_DEV_HSMMC
exynos4_default_sdhci0();
#endif
#ifdef CONFIG_S3C_DEV_HSMMC1
exynos4_default_sdhci1();
#endif
#ifdef CONFIG_S3C_DEV_HSMMC2
exynos4_default_sdhci2();
#endif
#ifdef CONFIG_S3C_DEV_HSMMC3
exynos4_default_sdhci3();
#endif
#ifdef CONFIG_EXYNOS4_DEV_MSHC
exynos4_default_mshci();
#endif
exynos4_i2sv3_setup_resource();
s3c_fimc_setname(0, "exynos4-fimc");
s3c_fimc_setname(1, "exynos4-fimc");
s3c_fimc_setname(2, "exynos4-fimc");
s3c_fimc_setname(3, "exynos4-fimc");
#ifdef CONFIG_S3C_DEV_RTC
s3c_rtc_setname("exynos-rtc");
#endif
#ifdef CONFIG_FB_S3C
s5p_fb_setname(0, "exynos4-fb"); /* FIMD0 */
#endif
if (soc_is_exynos4210())
s3c_adc_setname("samsung-adc-v3");
else
s3c_adc_setname("samsung-adc-v4");
s5p_hdmi_setname("exynos4-hdmi");
/* The I2C bus controllers are directly compatible with s3c2440 */
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_i2c2_setname("s3c2440-i2c");
#ifdef CONFIG_S5P_DEV_ACE
s5p_ace_setname("exynos4-ace");
#endif
}
static inline void __iomem *cpu_boot_reg_base(void)
{
if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
return S5P_INFORM5;
else if (soc_is_exynos5440())
return S5P_VA_CHIPID + 0x560;
return sysram_base_addr;
}
int __init exynos5_jpeg_setup_clock(struct device *dev,
unsigned long clk_rate)
{
struct clk *sclk;
struct clk *mout_user = NULL;
int ret;
sclk = clk_get(dev, "sclk_jpeg");
if (IS_ERR(sclk))
return PTR_ERR(sclk);
if (samsung_rev() >= EXYNOS5250_REV_1_0) {
mout_user = clk_get(dev, "mout_mpll_user");
if (IS_ERR(mout_user))
return PTR_ERR(mout_user);
ret = clk_set_parent(sclk, mout_user);
if (ret < 0) {
dev_err(dev, "failed to clk_set_parent for jpeg\n");
goto err_clk;
}
}
if (!clk_rate)
clk_rate = 150000000UL;
if (clk_set_rate(sclk, clk_rate)) {
pr_err("%s rate change failed: %lu\n", sclk->name, clk_rate);
clk_put(sclk);
return PTR_ERR(sclk);
}
clk_put(sclk);
if (samsung_rev() >= EXYNOS5250_REV_1_0)
clk_put(mout_user);
return 0;
if (samsung_rev() >= EXYNOS5250_REV_1_0) {
err_clk:
clk_put(mout_user);
return -EINVAL;
}
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{
int i;
if (soc_is_exynos4210() || soc_is_exynos4212() || soc_is_exynos4412())
scu_enable(scu_base_addr());
for (i = 1; i < max_cpus; i++) {
int pwr_offset = 0;
#ifdef CONFIG_ARM_TRUSTZONE
cpu_boot_info[i].boot_base = S5P_VA_SYSRAM_NS + 0x1C;
#else
if (soc_is_exynos4210() &&
(samsung_rev() >= EXYNOS4210_REV_1_1))
cpu_boot_info[i].boot_base = EXYNOS_INFORM5;
else
cpu_boot_info[i].boot_base = S5P_VA_SYSRAM;
#endif
if (soc_is_exynos4412())
cpu_boot_info[i].boot_base += (0x4 * i);
else if (soc_is_exynos5410()) {
int cluster_id = read_cpuid_mpidr() & 0x100;
if (samsung_rev() < EXYNOS5410_REV_1_0) {
if (cluster_id == 0)
pwr_offset = 4;
} else {
if (cluster_id != 0)
pwr_offset = 4;
}
}
cpu_boot_info[i].power_base =
EXYNOS_ARM_CORE_CONFIGURATION(i + pwr_offset);
}
}
static ssize_t hw_get_version(struct device *dev,
struct device_attribute *attr, char *buf)
{
int hw_ver = 0;
int temp = 0;
temp = samsung_rev();
printk("====%s:hw id is 0x%02x====\n", __func__, temp);
if (temp <= EXYNOS4412_REV_1_1)
hw_ver = 1;
else
hw_ver = 0;
return sprintf(buf, "%d\n", hw_ver);
}
static void __init smdk5250_ehci_init(void)
{
struct s5p_ehci_platdata *pdata = &smdk5250_ehci_pdata;
#ifndef CONFIG_USB_EXYNOS_SWITCH
if (samsung_rev() >= EXYNOS5250_REV_1_0) {
if (gpio_request_one(EXYNOS5_GPX2(6), GPIOF_OUT_INIT_HIGH,
"HOST_VBUS_CONTROL"))
printk(KERN_ERR "failed to request gpio_host_vbus\n");
else {
s3c_gpio_setpull(EXYNOS5_GPX2(6), S3C_GPIO_PULL_NONE);
gpio_free(EXYNOS5_GPX2(6));
}
}
#endif
s5p_ehci_set_platdata(pdata);
}
static mali_bool mali_dvfs_table_update(void)
{
unsigned int i;
unsigned int step_num = MALI_DVFS_STEPS;
if(samsung_rev() < EXYNOS4412_REV_2_0)
step_num = MALI_DVFS_STEPS - 1;
if(soc_is_exynos4412()) {
for (i = 0; i < step_num; i++) {
MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv));
mali_dvfs[i].vol = asv_3d_volt_9_table[i][exynos_result_of_asv];
MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol));
}
}
return MALI_TRUE;
}
static mali_bool set_mali_dvfs_status(u32 step,mali_bool boostup)
{
u32 validatedStep=step;
#ifdef CONFIG_REGULATOR
if (mali_regulator_get_usecount() == 0) {
MALI_DEBUG_PRINT(1, ("regulator use_count is 0 \n"));
return MALI_FALSE;
}
#endif
if (boostup) {
#ifdef CONFIG_REGULATOR
/*change the voltage*/
mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
/*change the clock*/
mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
} else {
/*change the clock*/
mali_clk_set_rate(mali_dvfs[step].clock, mali_dvfs[step].freq);
#ifdef CONFIG_REGULATOR
/*change the voltage*/
mali_regulator_set_voltage(mali_dvfs[step].vol, mali_dvfs[step].vol);
#endif
}
#ifdef EXYNOS4_ASV_ENABLED
if (samsung_rev() < EXYNOS4412_REV_2_0) {
if (mali_dvfs[step].clock == 160)
exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_100V);
else
exynos4x12_set_abb_member(ABB_G3D, ABB_MODE_130V);
}
#endif
set_mali_dvfs_current_step(validatedStep);
/*for future use*/
maliDvfsStatus.pCurrentDvfs = &mali_dvfs[validatedStep];
return MALI_TRUE;
}