static void sata_init(struct device *dev)
{
sb_config->StdHeader.Func = SB_MID_POST_INIT;
AmdSbDispatcher(sb_config); //sataInitMidPost only
commonInitLateBoot(sb_config);
sataInitLatePost(sb_config);
}
/*********************************************************************************
*
* Routine Description: Config SB after ACPI S3 resume PCI config device restore
*
* Arguments:
*
* pConfig - SBconfiguration
*
* Returns: void
*
* Reference: AtiSbAfPciRestore
*
**********************************************************************************/
void sbAfterPciRestoreInit(AMDSBCFG* pConfig){
BUILDPARAM *pStaticOptions;
pConfig->S3Resume = 1;
pStaticOptions = &pConfig->BuildParameters;
TRACE((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
commonInitLateBoot(pConfig);
sataInitAfterPciEnum(pConfig);
azaliaInitAfterPciEnum(pConfig); // Detect and configure High Definition Audio
hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit
sataInitLatePost(pConfig);
sbSmmAcpiOn(pConfig);
}
/*********************************************************************************
*
* Routine Description: Config SB during late POST
*
* Arguments:
*
* pConfig - SBconfiguration
*
* Returns: void
*
* Reference: atiSbLatePost
*
**********************************************************************************/
void sbLatePost(AMDSBCFG* pConfig){
UINT16 dwVar;
BUILDPARAM *pStaticOptions;
pStaticOptions = &pConfig->BuildParameters;
TRACE((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
ReadPCI((SMBUS_BUS_DEV_FUN << 16) + SB_SMBUS_REG02, AccWidthUint16, &dwVar);
if (dwVar != SB7XX_DEVICE_ID){
// Display message that the SB is wrong and stop the system
TRACE((DMSG_SB_TRACE, "Current system does not have SB700 chipset. Stopping\n"));
for(;;);
}
commonInitLateBoot(pConfig);
sataInitLatePost(pConfig);
hpetInit(pConfig, pStaticOptions); // SB Configure HPET base and enable bit
#ifndef NO_EC_SUPPORT
ecInitLatePost(pConfig);
#endif
}
/**
* sbLatePost - Prepare Southbridge to boot to OS.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbLatePost (
IN AMDSBCFG* pConfig
)
{
// UINT16 dwVar;
BUILDPARAM *pStaticOptions;
pStaticOptions = &(pConfig->BuildParameters);
commonInitLateBoot (pConfig);
sataInitLatePost (pConfig);
gecInitLatePost (pConfig);
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
#ifndef NO_EC_SUPPORT
ecInitLatePost (pConfig);
#endif
sbPcieGppLateInit (pConfig);
}
VOID
sbAfterPciRestoreInit (
IN AMDSBCFG* pConfig
)
{
BUILDPARAM *pStaticOptions;
pConfig->S3Resume = 1;
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
pStaticOptions = &(pConfig->BuildParameters);
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbAfterPciRestoreInit \n"));
commonInitLateBoot (pConfig);
sataInitAfterPciEnum (pConfig);
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
sataInitLatePost (pConfig);
c3PopupSetting (pConfig);
RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REG00, AccWidthUint8, 0xFF, 0x1E);
hwmInit (pConfig);
hwmImcInit (pConfig);
}
/**
* sbLatePost - Prepare Southbridge to boot to OS.
*
*
*
* @param[in] pConfig Southbridge configuration structure pointer.
*
*/
VOID
sbLatePost (
IN AMDSBCFG* pConfig
)
{
// UINT16 dwVar;
BUILDPARAM *pStaticOptions;
pStaticOptions = &(pConfig->BuildParameters);
TRACE ((DMSG_SB_TRACE, "CIMx - Entering sbLatePost \n"));
commonInitLateBoot (pConfig);
sataInitLatePost (pConfig);
gecInitLatePost (pConfig);
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
#ifndef NO_EC_SUPPORT
ecInitLatePost (pConfig);
#endif
sbPcieGppLateInit (pConfig);
hwmImcInit (pConfig);
// hwmSbtsiAutoPollingOff (pConfig);
imcDisarmSurebootTimer (pConfig);
usbInitLate (pConfig); // Init USB
StressResetModeLate (pConfig); //
}
VOID
sbAfterPciRestoreInit (
IN AMDSBCFG* pConfig
)
{
BUILDPARAM *pStaticOptions;
pConfig->S3Resume = 1;
usbSetPllDuringS3 (pConfig);
pStaticOptions = &(pConfig->BuildParameters);
commonInitLateBoot (pConfig);
sataInitAfterPciEnum (pConfig);
gecInitAfterPciEnum (pConfig);
azaliaInitAfterPciEnum (pConfig); // Detect and configure High Definition Audio
hpetInit (pConfig, pStaticOptions); // SB Configure HPET base and enable bit
sataInitLatePost (pConfig);
c3PopupSetting (pConfig);
#ifndef NO_HWM_SUPPORT
SBIMCFanInitializeS3 ();
#endif
}