INLINE void saturn_instruction_0e(saturn_state *cpustate)
{
int reg, adr;
switch(adr=READ_OP(cpustate)) {
case 0:
switch(reg=READ_OP(cpustate)){
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
saturn_and(cpustate, reg_left[reg], cpustate->p, 1, reg_right[reg]);
break; //A=A&B p
case 8: case 9: case 0xa: case 0xb: case 0xc: case 0xd: case 0xe: case 0xf:
saturn_or(cpustate, reg_left[reg&7], cpustate->p, 1, reg_right[reg&7]);
break; //A=A!B p
}
break;
case 1:
switch(reg=READ_OP(cpustate)){
case 0: case 1: case 2: case 3:case 4: case 5: case 6: case 7:
saturn_and(cpustate, reg_left[reg], 0, cpustate->p+1, reg_right[reg]);
break; //A=A&B wp
case 8: case 9: case 0xa: case 0xb: case 0xc: case 0xd: case 0xe: case 0xf:
saturn_or(cpustate, reg_left[reg&7], 0, cpustate->p+1, reg_right[reg&7]);
break; //A=A!B wp
}
break;
case 2: case 3: case 4: case 5: case 6: case 7: case 0xf:
switch(reg=READ_OP(cpustate)){
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
saturn_and(cpustate, reg_left[reg], adr_af_begin[adr], adr_af_count[adr], reg_right[reg]);
break; //A=A&B xs
case 8: case 9: case 0xa: case 0xb: case 0xc: case 0xd: case 0xe: case 0xf:
saturn_or(cpustate, reg_left[reg&7], adr_af_begin[adr], adr_af_count[adr], reg_right[reg&7]);
break; //A=A!B xs
}
break;
default:
saturn_invalid3( cpustate, 0, 0xe, adr );
break;
}
}
INLINE void saturn_instruction_0e(void)
{
int reg, adr;
switch(adr=READ_OP()) {
case 0:
switch(reg=READ_OP()){
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
saturn_and(reg_left[reg], saturn.p, 1, reg_right[reg]);
break; /*A=A&B p */
case 8: case 9: case 0xa: case 0xb: case 0xc: case 0xd: case 0xe: case 0xf:
saturn_or(reg_left[reg&7], saturn.p, 1, reg_right[reg&7]);
break; /*A=A!B p */
}
break;
case 1:
switch(reg=READ_OP()){
case 0: case 1: case 2: case 3:case 4: case 5: case 6: case 7:
saturn_and(reg_left[reg], 0, saturn.p+1, reg_right[reg]);
break; /*A=A&B wp */
case 8: case 9: case 0xa: case 0xb: case 0xc: case 0xd: case 0xe: case 0xf:
saturn_or(reg_left[reg&7], 0, saturn.p+1, reg_right[reg&7]);
break; /*A=A!B wp */
}
break;
case 2: case 3: case 4: case 5: case 6: case 7: case 0xf:
switch(reg=READ_OP()){
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
saturn_and(reg_left[reg], adr_af_begin[adr], adr_af_count[adr], reg_right[reg]);
break; /*A=A&B xs */
case 8: case 9: case 0xa: case 0xb: case 0xc: case 0xd: case 0xe: case 0xf:
saturn_or(reg_left[reg&7], adr_af_begin[adr], adr_af_count[adr], reg_right[reg&7]);
break; /*A=A!B xs */
}
break;
}
}