int sc_main(int argc, char* argv[]) {
sc_signal<bool> Din;
sc_signal< sc_uint<4> > r;
sc_clock TestClk("TestClock", 10, SC_NS,0,SC_NS);
stim Stim1("Stimulus");
Stim1.Din(Din);
sr SR1("SR1");
SR1.din(Din);
SR1.clk(TestClk);
SR1.r(r);
mon Monitor1("Monitor");
Monitor1.Din(Din);
Monitor1.r(r);
Monitor1.Clk(TestClk);
sc_start(); // run forever
return 0;
}
int sc_main(int argc,char ** argv)
{
try
{
wireworld_common::wireworld_configuration l_config;
wireworld_common::wireworld_types::t_cell_list l_copper_cells;
wireworld_common::wireworld_types::t_cell_list l_tail_cells;
wireworld_common::wireworld_types::t_cell_list l_electron_cells;
wireworld_common::wireworld_types::t_cell_list l_inactive_cells;
wireworld_common::wireworld_types::t_neighbours l_neighbours;
uint32_t l_x_max = 0;
uint32_t l_y_max = 0;
wireworld_common::wireworld_prepare::prepare(argc,argv,
l_config,
l_copper_cells,
l_tail_cells,
l_electron_cells,
l_inactive_cells,
l_neighbours,
l_x_max,
l_y_max);
wireworld_systemc::top l_top("top",l_copper_cells,l_tail_cells,l_electron_cells,l_config,l_x_max,l_y_max,l_inactive_cells,l_neighbours);
sc_start();
}
catch(quicky_exception::quicky_logic_exception & e)
{
std::cout << "ERROR : Runtime exception : " << e.what() << std::endl ;
return -1;
}
catch(quicky_exception::quicky_runtime_exception & e)
{
std::cout << "ERROR : Runtime exception : " << e.what() << std::endl ;
return -1;
}
return 0;
}
int sc_main(int ac, char *av[])
{
// Signal Instantiation
sc_signal<bool> reset ("reset");
sc_signal<bool> prime_ready ("prime_ready");
signal_bool_vector prime ("prime");
// Clock Instantiation
sc_clock clk ("CLK", 6, SC_NS, 0.5, 10, SC_NS, false); // 167 Mhz
// Process Instantiation
prime_numgen D1 ("D1", clk, reset, prime_ready, prime);
resetp T1 ("T1", clk, reset);
displayp T2 ("T2", clk, prime_ready, prime);
// Simulation Run Control
sc_start();
return 0;
}
/**
* SystemC main
*/
int sc_main(int argc, char* argv[]) {
if(argc == 1)
cout << "No Argument ! " << endl;
// ELABORATION Phase
if(argc >= 2)
cout << " First Argument : " << argv[1] << endl;
if(argc >= 3)
cout << " Second Argument : " << argv[2] << endl;
sc_start(); // SIMULATION begins and ends in this function
system("pause");
return 0; // EXIT CODE (0 = success)
}
int
sc_main(int argc, char* argv[])
{
sc_signed x(7);
x = -34;
cout << x << endl;
x.dump(cout);
for (int i = 0; i < 5; ++i) {
sc_signed y(7);
y = x >> i;
cout << y << endl;
y.dump(cout);
}
for (int i = 0; i < 5; ++i) {
x = x >> 1;
cout << x << endl;
x.dump(cout);
}
sc_start(0, SC_NS);
return 0;
}
int sc_main (int argc, char *argv[] )
{
sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
sc_set_time_resolution(1,SC_NS);
TLL6219::bootConfig bc = TLL6219::BCONF_LINUX;
int i;
for(i=1; i < argc; i++) {
if (strcmp(argv[i], "u") == 0) {
bc = TLL6219::BCONF_UBOOT;
} else if (strcmp(argv[i], "l") == 0) {
bc = TLL6219::BCONF_LINUX;
} else if (strcmp(argv[i], "b") == 0) {
bc = TLL6219::BCONF_BAREMETAL;
} else {
cout << "Usage: TLL_tlm2.0.exe [u|l|b]" << endl;
cout << " u = U-Boot: l = Linux: b = Bare metal" << endl;
exit(0);
break;
}
}
// Ignore some of the Warning messages
icmIgnoreMessage ("ICM_NPF");
cout << "Constructing." << endl;
TLL5000 top("top", bc);
cout << "default time resolution = " << sc_get_time_resolution() << endl;
// start the simulation
cout << "Starting sc_main." << endl;
sc_start();
cout << "Finished sc_main." << endl;
return 0; // return okay status
}
int
sc_main( int argc, char* argv[] )
{
sc_signal<int> a("a");
sc_signal<int> b("b");
sc_signal<int> c("c");
sc_clock clk("clk", 10, SC_NS);
example ex1("ex1");
ex1(clk, a, b, c);
tb tbb1("tbb1");
tbb1(clk, a);
tb2 tbb2("tbb2");
tbb2(clk, b);
monitor mon("mon", a, b, c);
sc_start(200, SC_NS);
return 0;
}
int
sc_main(int ac, char *av[])
{
// Signal Instantiation
sc_signal<int> in1 ("in1");
sc_signal<int> in2 ("in2");
sc_signal<int> result ("result");
sc_signal<bool> ready ("ready");
// Clock Instantiation
sc_clock clk( "clock", 10, SC_NS, 0.5, 0, SC_NS);
// Process Instantiation
datawidth D1 ("D1", clk, in1, in2, ready, result);
stimgen T1 ("T1", clk, result, in1, in2, ready);
// Simulation Run Control
sc_start();
return 0;
}
int sc_main(int argc, char * argv[]) {
try {
//Instantiate Modules
Memory mem("main_memory");
CPU cpu("cpu");
//Signals
sc_buffer<Memory::Function> sigMemFunc;
sc_buffer<Memory::RetCode> sigMemDone;
sc_signal<int> sigMemAddr;
sc_signal_rv<32> sigMemData;
// The clock that will drive the CPU and Memory
sc_clock clk;
// Connecting module ports with signals
mem.Port_Func(sigMemFunc);
mem.Port_Addr(sigMemAddr);
mem.Port_Data(sigMemData);
mem.Port_Done(sigMemDone);
cpu.Port_MemFunc(sigMemFunc);
cpu.Port_MemAddr(sigMemAddr);
cpu.Port_MemData(sigMemData);
cpu.Port_MemDone(sigMemDone);
mem.Port_CLK(clk);
cpu.Port_CLK(clk);
cout << "Installing trace signals. Output in ram_trace.vcd " << endl;
sc_trace_file *wf = sc_create_vcd_trace_file("ram_trace");
sc_trace(wf, clk, "clock");
sc_trace(wf, sigMemFunc, "function");
sc_trace(wf, sigMemAddr, "sigMemAddr");
sc_trace(wf, sigMemData, "sigMemData");
cout << " Running (press CTRL + C to exit)... " << endl;
// Start Simulation
sc_start();
} catch (const std::exception & e) {
cerr << e.what() << endl;
}
return 0;
}
int sc_main(int ac, char *av[])
{
sc_signal<double> in1;
sc_signal<double> in2;
sc_signal<double> sum;
sc_signal<double> diff;
sc_signal<double> prod;
sc_signal<double> quot;
sc_signal<double> powr;
powr = 0.0;
sc_clock clk("CLOCK", 20.0, SC_NS, 0.5, 0.0, SC_NS);
numgen N("STIMULUS", clk, in1, in2);
stage1 S1("Stage1", clk, in1, in2, sum, diff);
stage2 S2("Stage2", clk, sum, diff, prod, quot);
stage3 S3("Stage3", clk, prod, quot, powr);
display D("Display", clk, powr);
sc_start(1000, SC_NS);
return 0;
}
int sc_main (int argc , char *argv[]) {
sc_clock clock;
sc_signal<bool> reset;
sc_signal<bool> out_valid;
sc_signal<bool> in_valid;
sc_signal<int> result;
sc_signal<int> in_value;
while_datatypes while_datatypes1 (
"process_body",
clock,
reset,
in_valid,
in_value,
out_valid,
result
);
stimulus stimulus1 (
"stimulus",
clock,
reset,
in_value,
in_valid
);
display display1 (
"display",
clock,
result,
out_valid
);
sc_start();
return 0;
}
int sc_main(int argn,char* argc[])
{
sca_tdf::sca_signal<double> sig_1, sig_2;
sca_tdf::sca_signal<bool> sig_3;
sin_source_with_noise sin1("sin1");
sin1.out(sig_1);
prefilter prefi1("lp1");
prefi1.in(sig_1);
prefi1.out(sig_2);
adc_sd adc1("adc1");
adc1.in(sig_2);
adc1.out(sig_3);
sca_trace_file* tfp =
sca_create_vcd_trace_file("tb_lab2c");
sca_trace(tfp, sig_1, "sig_1");
sca_trace(tfp, sig_2, "sig_2");
sca_trace(tfp, sig_3, "sig_3");
sc_start(5.0, SC_MS);
sca_close_vcd_trace_file(tfp);
tfp = sca_create_tabular_trace_file("tb_ac_lab2c.dat");
tfp->set_mode(sca_ac_format(sca_util::SCA_AC_DB_DEG));
sca_trace(tfp, sig_1, "sig_1");
sca_trace(tfp, sig_2, "sig_2");
sca_trace(tfp, sig_3, "sig_3");
sca_ac_start(1.0, 1e6, 1000, SCA_LOG);
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<bool> XSig, YSig,ZSig,SSig,CSig;
sc_clock TestClk("TestClock", 10, SC_NS,1,SC_NS);
// sc_trace_file *tf = sc_create_vcd_trace_file("trace");
stim Stim1("Stimulus");
Stim1.X(XSig);
Stim1.Y(YSig);
Stim1.Z(ZSig);
Stim1.Clk(TestClk);
adder A1("A");
A1.a(XSig);
A1.b(YSig);
A1.c(ZSig);
A1.carry(CSig);
A1.sum(SSig);
/*
sc_trace(tf,XSig,"X");
sc_trace(tf,YSig,"Y");
sc_trace(tf,ZSig,"Z");
sc_trace(tf,SSig,"S");
sc_trace(tf,CSig,"C");
*/
mon Monitor1("Monitor");
Monitor1.X(XSig);
Monitor1.Y(YSig);
Monitor1.Z(ZSig);
Monitor1.S(SSig);
Monitor1.C(CSig);
Monitor1.Clk(TestClk);
// sc_close_vcd_trace_file(tf);
sc_start(); // run forever
return 0;
}
int sc_main( int argc, char *argv[] ) {
// Signals
sc_signal<int> arg1;
sc_signal<int> arg2;
sc_signal<int> sum;
// Clock
sc_clock clk( "clock", 10, 0.5 );
// Module
stimuli *S;
adder *A;
display *D;
// Module instantiations and Mapping
S = new stimuli("stimuli");
//(*S) (arg1, arg2, clk);
A = new adder("adder");
//(*A) (arg1, arg2, sum);
D = new display ("display");
//(*D) (sum);
S->clk(clk);
S->out1(arg1);
S->out2(arg2);
A->clk(clk);
A->in1(arg1);
A->in2(arg2);
A->out1(sum);
D->clk(clk);
D->in1(sum);
// Start of the Simulation
sc_start(200);
return 0;
};
int sc_main(int argc, char *argv[])
{
sc_signal<int> s1, s2;
sc_clock clk("c1", 1, SC_NS);
top top1("Top1");
top1.clk(clk);
top1.input(s1);
top1.output(s2);
stimulus sti1("stimulus1");
sti1.clk(clk);
sti1.x(s1);
monitor mon1("monitor1");
mon1.clk(clk);
mon1.z(s2);
sc_start(20, SC_NS);
return 0;
}
int sc_main(int argc, char *argv[]) {
//sc_report_handler::set_actions("/IEEE_Std_1666/deprecated", SC_DO_NOTHING);
disable_T();
TOP *inst_top_arm = new TOP("Top");
clock_t TimeStart = clock ();
sc_start(-1);
clock_t TimeStop = clock ();
delete inst_top_arm;
cout << endl << "CPU time: "
<< difftime (TimeStop, TimeStart) / CLOCKS_PER_SEC << " sec"
<< endl << endl;
return 0;
}
int sc_main(int argc, char* argv[]){
sc_time PERIOD(10,SC_NS); // NS, SEC, SC
sc_time DELAY(10,SC_NS);
sc_clock clock("clock", PERIOD, 0.5, DELAY, true);
Not_Gate ag1("ag1");
TestBench tb("tb");
sc_signal<bool> a_sg, z_sg;
ag1.a_in(a_sg);
ag1.z_out(z_sg);
tb.clk_in(clock);
tb.a_out(a_sg);
tb.z_in(z_sg);
sc_start();
return 0;
}
int sc_main (int argc, char* argv[]) {
sc_signal<unsigned int> data;
sc_signal<unsigned int> addr_last;
sc_signal<unsigned int> address;
sc_signal<bool> we,ce;
memory mem1("mem1", 1040,"T1.txt");
tb_mem test1("test1");
mem1.ce(ce);
mem1.we(we);
mem1.data(data);
mem1.addr_last(addr_last);
mem1.address(address);
test1.ce(ce);
test1.we(we);
test1.data(data);
test1.addr_last(addr_last);
test1.address(address);
sc_start();
return 0;
}
int sc_main(int argc, char* argv[]) {
cout << "INFO: Elaborating ..." << endl;
sc_set_time_resolution(100,SC_PS);
sc_time period(2,SC_NS);
generator clock("clock", period);
test_generator test_generator_i("test_generator_i");
test_generator_i.clock(clock);
cout << "INFO: Simulating " << endl;
sc_start(20, SC_NS);
cout << "INFO: Post-processing ... " << endl;
system("pause");
return 0;
}
int sc_main(int ac, char *av[])
{
//! ISA simulator
mips mips_proc1("mips");
//! Bus
ac_tlm_bus bus("bus");
// Memory
ac_tlm_mem mem("mem");
#ifdef AC_DEBUG
ac_trace("mips1_proc1.trace");
#endif
mips_proc1.DM(bus.target_export);
bus.MEM_port(mem.target_export);
mips_proc1.init(ac, av);
mips_proc1.set_prog_args();
cerr << endl;
sc_start();
mips_proc1.PrintStat();
cerr << endl;
#ifdef AC_STATS
mips1_proc1.ac_sim_stats.time = sc_simulation_time();
mips1_proc1.ac_sim_stats.print();
#endif
#ifdef AC_DEBUG
ac_close_trace();
#endif
return mips_proc1.ac_exit_status;
}
int sc_main(int argc, char* argv[]) {
sc_signal<bool> enable, rw, clr;
sc_clock clk("clk",10,SC_NS);
sc_signal<sc_uint<32> > din, dout;
sc_trace_file *fp; // VCD filepointer
fp=sc_create_vcd_trace_file("wave");// Create wave.vcd file
sc_trace(fp,clk,"clk"); // Add signals to trace file
sc_trace(fp,enable,"enable");
sc_trace(fp,rw,"rw");
sc_trace(fp,clr,"clr");
sc_trace(fp,din,"din");
sc_trace(fp,dout,"dout");
//register
reg REG("reg");
REG.clk(clk);
REG.enable(enable);
REG.rw(rw);
REG.clr(clr);
REG.din(din);
REG.dout(dout);
//stim
stim STIM("stim");
STIM.clk(clk);
STIM.enable(enable);
STIM.rw(rw);
STIM.clr(clr);
STIM.din(din);
sc_start(1000, SC_NS); //start simulation
sc_close_vcd_trace_file(fp); // close wave.vcd
return 0; // Return OK, no errors.
}
int sc_main (int argc , char *argv[]) {
// FIFO size can be set as command line argument
// default is 10
int size = 10;
if (argc > 1)
size = atoi(argv[1]);
if (size < 1)
size = 1;
if (size > 100000)
size = 100000;
// instantiating top module
top top1("Top1", size);
// initializing random number generator
srand ( time(NULL) );
// run simualtion indefinitely until some module calls sc_stop
sc_start();
return 0;
}
int sc_main(int argc, char* argv[]) {
sc_signal<sc_lv<1>> X_in,Y_in,Ci_in;
sc_signal<sc_lv<1>> S_out,C_out;
sc_clock CLK("clock",10,SC_NS);
fullAdder FA("FA");
FA(X_in,Y_in,Ci_in,S_out,C_out);
test TEST("TEST");
TEST(CLK,X_in,Y_in,Ci_in,S_out,C_out);
sc_trace_file *tf = sc_create_vcd_trace_file("wave");
sc_trace(tf,CLK,"clock");
sc_trace(tf,X_in,"X_in");
sc_trace(tf,Y_in,"Y_in");
sc_trace(tf,Ci_in,"Ci_in");
sc_trace(tf,S_out,"S_out");
sc_trace(tf,C_out,"C_out");
sc_start(80, SC_NS);
sc_close_vcd_trace_file(tf);
return(0);
}
int main() {
sc_signal<int> mem_add;
sc_signal<int> mem_data;
sc_signal<int> mem_we;
sc_signal<int> mem_ce;
Dram_Memory *dram;
dram = new Dram_Memory("dram");
generate *testb;
testb = new generate("testb");
dram->address(mem_add);
dram->data(mem_data);
dram->WE(mem_we);
dram->CE(mem_ce);
testb->t_address(mem_add);
testb->t_WE(mem_we);
testb->t_CE(mem_ce);
testb->t_data(mem_data);
check *testc;
testc = new check("testc");
testc->c_data(mem_data);
testc->c_address(mem_add);
testc->c_WE(mem_we);
testc->c_CE(mem_ce);
sc_report_handler::set_actions(SC_ID_VECTOR_CONTAINS_LOGIC_VALUE_,SC_DO_NOTHING);
sc_start(1500,SC_NS);
return 0;
}
int sc_main (int argc , char *argv[]) {
sc_clock clock;
sc_signal<bool> reset;
sc_signal<int> stimulus_line1;
sc_signal_bool_vector stimulus_line2;
sc_signal<bool> input_valid;
sc_signal<bool> output_valid;
sc_signal<int> result_line1;
sc_signal_bool_vector result_line2;
stimulus stimulus1("stimulus_block",
clock,
reset,
stimulus_line1,
stimulus_line2,
input_valid);
increment increment1 ( "process_body",
clock,
reset,
stimulus_line1,
stimulus_line2,
input_valid,
result_line1,
result_line2,
output_valid);
display display1 ( "display",
clock,
result_line1,
result_line2,
output_valid);
sc_start();
return 0;
}
int sc_main(int argc,char *argv[])
{
sc_time PERIOD(10,SC_NS);
sc_time DELAY(10,SC_NS);
sc_clock clock("clock",PERIOD,0.5,DELAY,true);
Xor_GateComp xorcomp_gate("xorcomp_gate");
TestBench test("test");
sc_signal<bool> a_sg, b_sg, c_sg; //Se declaran los 'cables' o señales que conectaran el modulo con el testbench
//Comienza la conexion entre el modulo y el testbench meidante los cables anteriormente declarados
xorcomp_gate.a_In_Xor(a_sg);
xorcomp_gate.b_In_Xor(b_sg);
xorcomp_gate.c_Out_Xor(c_sg);
test.Clock_In(clock);
test.c_In_Test(c_sg);
test.a_Out_Test(a_sg);
test.b_Out_Test(b_sg);
sc_start();
return 0;
}
int sc_main(int argc, char* argv[]){
sc_signal<bool> count_en; // triggers counting of the lfsr
sc_signal<bool> reset; // resets lfsr
sc_signal<sc_bv<8> > lfsrout; // with testbench module
sc_clock clk ("clk", 2, SC_US); // clock with a period of 2 µ-sec
lfsr lfsr_inst("lfsr_inst"); // instantiate a lfsr
stim stim_inst("stim_inst"); // and a testbench-module
lfsr_inst.clk(clk); // connect the lfsr ports to the
lfsr_inst.reset(reset); // appropriate signals
lfsr_inst.count_en(count_en);
lfsr_inst.out(lfsrout);
stim_inst.count_en(count_en); // connect the testbench ports to the
stim_inst.reset(reset); // appropriate signals
stim_inst.in(lfsrout);
sc_trace_file *tf; // Signal tracing
tf=sc_create_vcd_trace_file("lfsr"); // create new trace file
tf->set_time_unit(0.5,SC_US); // set time resolution to 0.5 µ-sec
sc_trace(tf,clk,"clk"); // trace each signal
sc_trace(tf,reset,"reset"); // trace each signal
sc_trace(tf,count_en,"count_en");
sc_trace(tf,lfsrout,"lfsrout");
sc_trace(tf,lfsr_inst.rightin,"rightin");
sc_start(700,SC_US); // run the simulation for 100 µ-sec
sc_close_vcd_trace_file(tf); // close trace file
return 0;
};
int sc_main(int argc, char* argv[]) {
sc_signal<bool> Write;
sc_signal < sc_uint<5> > rdAddrA,rdAddrB,wrAddr;
sc_signal < sc_uint<32> > rdDataA,rdDataB,wrData;
sc_clock TestClk("TestClock", 10, SC_NS,0,SC_NS);
stim Stim1("Stimulus");
Stim1.write(Write);
Stim1.rdAddrA(rdAddrA);
Stim1.rdAddrB(rdAddrB);
Stim1.wrAddr(wrAddr);
Stim1.wrData(wrData);
rf RF1("SR1");
RF1.write(Write);
RF1.clk(TestClk);
RF1.rdAddrA(rdAddrA);
RF1.rdAddrB(rdAddrB);
RF1.wrAddr(wrAddr);
RF1.rdDataA(rdDataA);
RF1.rdDataB(rdDataB);
RF1.wrData(wrData);
mon Monitor1("Monitor");
Monitor1.Clk(TestClk);
Monitor1.write(Write);
Monitor1.rdAddrA(rdAddrA);
Monitor1.rdAddrB(rdAddrB);
Monitor1.wrAddr(wrAddr);
Monitor1.rdDataA(rdDataA);
Monitor1.rdDataB(rdDataB);
Monitor1.wrData(wrData);
sc_start(); // run forever
return 0;
}
int sc_main(int ac, char *av[])
{
sc_fifo<int> st1("ST1", 2), st2("ST2", 2);
sc_fifo<int> a1("A1", 2), a2("A2", 2), a3("A3", 2);
sc_fifo<int> b1("B1", 2), b2("B2", 2), b3("B3", 2);
sc_clock clock("CLOCK");
sawtooth ST("TB1", clock, st1, st2);
delay D1("D1", clock, st1, a1);
downsample DN1("DN1", clock, a1, a2);
upsample UP1("UP1", clock, a2, a3);
downsample DN2("DN2", clock, st2, b1);
upsample UP2("UP2", clock, b1, b2);
delay D2("D2", clock, b2, b3);
adder A ("A", clock, a3, b3);
sc_start(100, SC_NS);
return 0;
}
int sc_main(int argc, char *argv[])
{
sc_signal<bool> t_enable;
sc_signal<sc_uint<2> > t_sel;
sc_signal<sc_uint<4> > t_z;
decoder d("decoder");
d.enable(t_enable);
d.select(t_sel);
d.z(t_z);
driver dr("driver");
dr.d_enable(t_enable);
dr.d_select(t_sel);
monitor mo("monitor");
mo.m_enable(t_enable);
mo.m_select(t_sel);
mo.m_z(t_z);
sc_start(100, SC_NS);
return (0);
}