static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = pltfm_host->priv; if (timing == MMC_TIMING_UHS_DDR50) tegra_host->ddr_signaling = true; return sdhci_set_uhs_signaling(host, timing); }
static void tegra_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); bool set_default_tap = false; bool set_dqs_trim = false; bool do_hs400_dll_cal = false; switch (timing) { case MMC_TIMING_UHS_SDR50: case MMC_TIMING_UHS_SDR104: case MMC_TIMING_MMC_HS200: /* Don't set default tap on tunable modes. */ break; case MMC_TIMING_MMC_HS400: set_dqs_trim = true; do_hs400_dll_cal = true; break; case MMC_TIMING_MMC_DDR52: case MMC_TIMING_UHS_DDR50: tegra_host->ddr_signaling = true; set_default_tap = true; break; default: set_default_tap = true; break; } sdhci_set_uhs_signaling(host, timing); tegra_sdhci_pad_autocalib(host); if (set_default_tap) tegra_sdhci_set_tap(host, tegra_host->default_tap); if (set_dqs_trim) tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim); if (do_hs400_dll_cal) tegra_sdhci_hs400_dll_cal(host); }