static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) { int start = 0, len = 0; int start_final = 0, len_final = 0; u8 final_phase = 0xFF; if (phase_map == 0) { dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); return final_phase; } while (start < RTSX_PHASE_MAX) { len = sd_get_phase_len(phase_map, start); if (len_final < len) { start_final = start; len_final = len; } start += len ? len : 1; } final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", phase_map, len_final, final_phase); return final_phase; }
static int sd_read_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, u8 *buf, int buf_len, int timeout) { struct rtsx_pcr *pcr = host->pcr; int err, i; u8 trans_mode; dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__, cmd[0] - 0x40); if (!buf) buf_len = 0; if ((cmd[0] & 0x3F) == MMC_SEND_TUNING_BLOCK) trans_mode = SD_TM_AUTO_TUNING; else trans_mode = SD_TM_NORMAL_READ; rtsx_pci_init_cmd(pcr); for (i = 0; i < 5; i++) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8)); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); if (trans_mode != SD_TM_AUTO_TUNING) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START); rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END); err = rtsx_pci_send_cmd(pcr, timeout); if (err < 0) { sd_print_debug_regs(host); dev_dbg(sdmmc_dev(host), "rtsx_pci_send_cmd fail (err = %d)\n", err); return err; } if (buf && buf_len) { err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); if (err < 0) { dev_dbg(sdmmc_dev(host), "rtsx_pci_read_ppbuf fail (err = %d)\n", err); return err; } } return 0; }
static int sd_write_data(struct realtek_pci_sdmmc *host, u8 *cmd, u16 byte_cnt, u8 *buf, int buf_len, int timeout) { struct rtsx_pcr *pcr = host->pcr; int err, i; u8 trans_mode; if (!buf) buf_len = 0; if (buf && buf_len) { err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); if (err < 0) { dev_dbg(sdmmc_dev(host), "rtsx_pci_write_ppbuf fail (err = %d)\n", err); return err; } } trans_mode = cmd ? SD_TM_AUTO_WRITE_2 : SD_TM_AUTO_WRITE_3; rtsx_pci_init_cmd(pcr); if (cmd) { dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d\n", __func__, cmd[0] - 0x40); for (i = 0; i < 5; i++) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0 + i, 0xFF, cmd[i]); } rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, (u8)byte_cnt); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, (u8)(byte_cnt >> 8)); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, 1); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, 0); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, trans_mode | SD_TRANSFER_START); rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END, SD_TRANSFER_END); err = rtsx_pci_send_cmd(pcr, timeout); if (err < 0) { sd_print_debug_regs(host); dev_dbg(sdmmc_dev(host), "rtsx_pci_send_cmd fail (err = %d)\n", err); return err; } return 0; }
static void sd_print_debug_regs(struct rtsx_usb_sdmmc *host) { struct rtsx_ucr *ucr = host->ucr; u8 val = 0; rtsx_usb_ep0_read_register(ucr, SD_STAT1, &val); dev_dbg(sdmmc_dev(host), "SD_STAT1: 0x%x\n", val); rtsx_usb_ep0_read_register(ucr, SD_STAT2, &val); dev_dbg(sdmmc_dev(host), "SD_STAT2: 0x%x\n", val); rtsx_usb_ep0_read_register(ucr, SD_BUS_STAT, &val); dev_dbg(sdmmc_dev(host), "SD_BUS_STAT: 0x%x\n", val); }
static int sd_change_phase(struct realtek_pci_sdmmc *host, u8 sample_point, bool rx) { struct rtsx_pcr *pcr = host->pcr; int err; dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", __func__, rx ? "RX" : "TX", sample_point); rtsx_pci_init_cmd(pcr); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, CHANGE_CLK); if (rx) rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPRX_CTL, 0x1F, sample_point); else rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPTX_CTL, 0x1F, sample_point); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, PHASE_NOT_RESET); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CHANGE_CLK, 0); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); err = rtsx_pci_send_cmd(pcr, 100); if (err < 0) return err; return 0; }
static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, bool is_first_req) { struct realtek_pci_sdmmc *host = mmc_priv(mmc); struct mmc_data *data = mrq->data; if (data->host_cookie) { dev_err(sdmmc_dev(host), "error: reset data->host_cookie = %d\n", data->host_cookie); data->host_cookie = 0; } sd_pre_dma_transfer(host, data, true); dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); }
/* * sd_pre_dma_transfer - do dma_map_sg() or using cookie * * @pre: if called in pre_req() * return: * 0 - do dma_map_sg() * 1 - using cookie */ static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, struct mmc_data *data, bool pre) { struct rtsx_pcr *pcr = host->pcr; int read = data->flags & MMC_DATA_READ; int count = 0; int using_cookie = 0; if (!pre && data->host_cookie && data->host_cookie != host->cookie) { dev_err(sdmmc_dev(host), "error: data->host_cookie = %d, host->cookie = %d\n", data->host_cookie, host->cookie); data->host_cookie = 0; } if (pre || data->host_cookie != host->cookie) { count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); } else { count = host->cookie_sg_count; using_cookie = 1; } if (pre) { host->cookie_sg_count = count; if (++host->cookie < 0) host->cookie = 1; data->host_cookie = host->cookie; } else { host->sg_count = count; } return using_cookie; }
static int sd_read_data(struct rtsx_usb_sdmmc *host, struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len, int timeout) { struct rtsx_ucr *ucr = host->ucr; int err; u8 trans_mode; if (!buf) buf_len = 0; rtsx_usb_init_cmd(ucr); if (cmd != NULL) { dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD%d\n", __func__ , cmd->opcode); if (cmd->opcode == MMC_SEND_TUNING_BLOCK) trans_mode = SD_TM_AUTO_TUNING; else trans_mode = SD_TM_NORMAL_READ; rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CMD0, 0xFF, (u8)(cmd->opcode) | 0x40); rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(cmd->arg >> 24)); rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(cmd->arg >> 16)); rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(cmd->arg >> 8)); rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)cmd->arg); } else {
static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) { struct rtsx_pcr *pcr = host->pcr; u16 i; u8 *ptr; /* Print SD host internal registers */ rtsx_pci_init_cmd(pcr); for (i = 0xFDA0; i <= 0xFDAE; i++) rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); for (i = 0xFD52; i <= 0xFD69; i++) rtsx_pci_add_cmd(pcr, READ_REG_CMD, i, 0, 0); rtsx_pci_send_cmd(pcr, 100); ptr = rtsx_pci_get_cmd_data(pcr); for (i = 0xFDA0; i <= 0xFDAE; i++) dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); for (i = 0xFD52; i <= 0xFD69; i++) dev_dbg(sdmmc_dev(host), "0x%04X: 0x%02x\n", i, *(ptr++)); }
static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) { int err, i; u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; u8 final_phase; for (i = 0; i < RX_TUNING_CNT; i++) { err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); if (err < 0) return err; if (raw_phase_map[i] == 0) break; } phase_map = 0xFFFFFFFF; for (i = 0; i < RX_TUNING_CNT; i++) { dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", i, raw_phase_map[i]); phase_map &= raw_phase_map[i]; } dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); if (phase_map) { final_phase = sd_search_final_phase(host, phase_map); if (final_phase == 0xFF) return -EINVAL; err = sd_change_phase(host, final_phase, true); if (err < 0) return err; } else { return -EINVAL; } return 0; }
static void sd_request(struct work_struct *work) { struct realtek_pci_sdmmc *host = container_of(work, struct realtek_pci_sdmmc, work); struct rtsx_pcr *pcr = host->pcr; struct mmc_host *mmc = host->mmc; struct mmc_request *mrq = host->mrq; struct mmc_command *cmd = mrq->cmd; struct mmc_data *data = mrq->data; unsigned int data_size = 0; int err; if (host->eject) { cmd->error = -ENOMEDIUM; goto finish; } err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); if (err) { cmd->error = err; goto finish; } mutex_lock(&pcr->pcr_mutex); rtsx_pci_start_run(pcr); rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, host->initial_mode, host->double_clk, host->vpclk); rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); rtsx_pci_write_register(pcr, CARD_SHARE_MODE, CARD_SHARE_MASK, CARD_SHARE_48_SD); mutex_lock(&host->host_mutex); host->mrq = mrq; mutex_unlock(&host->host_mutex); if (mrq->data) data_size = data->blocks * data->blksz; if (!data_size || sd_rw_cmd(cmd)) { sd_send_cmd_get_rsp(host, cmd); if (!cmd->error && data_size) { sd_rw_multi(host, mrq); if (!host->using_cookie) sdmmc_post_req(host->mmc, host->mrq, 0); if (mmc_op_multi(cmd->opcode) && mrq->stop) sd_send_cmd_get_rsp(host, mrq->stop); } } else { sd_normal_rw(host, mrq); } if (mrq->data) { if (cmd->error || data->error) data->bytes_xfered = 0; else data->bytes_xfered = data->blocks * data->blksz; } mutex_unlock(&pcr->pcr_mutex); finish: if (cmd->error) dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error); mutex_lock(&host->host_mutex); host->mrq = NULL; mutex_unlock(&host->host_mutex); mmc_request_done(mmc, mrq); }
static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, struct mmc_command *cmd) { struct rtsx_pcr *pcr = host->pcr; u8 cmd_idx = (u8)cmd->opcode; u32 arg = cmd->arg; int err = 0; int timeout = 100; int i; u8 *ptr; int stat_idx = 0; u8 rsp_type; int rsp_len = 5; bool clock_toggled = false; dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", __func__, cmd_idx, arg); /* Response type: * R0 * R1, R5, R6, R7 * R1b * R2 * R3, R4 */ switch (mmc_resp_type(cmd)) { case MMC_RSP_NONE: rsp_type = SD_RSP_TYPE_R0; rsp_len = 0; break; case MMC_RSP_R1: rsp_type = SD_RSP_TYPE_R1; break; case MMC_RSP_R1 & ~MMC_RSP_CRC: rsp_type = SD_RSP_TYPE_R1 | SD_NO_CHECK_CRC7; break; case MMC_RSP_R1B: rsp_type = SD_RSP_TYPE_R1b; break; case MMC_RSP_R2: rsp_type = SD_RSP_TYPE_R2; rsp_len = 16; break; case MMC_RSP_R3: rsp_type = SD_RSP_TYPE_R3; break; default: dev_dbg(sdmmc_dev(host), "cmd->flag is not valid\n"); err = -EINVAL; goto out; } if (rsp_type == SD_RSP_TYPE_R1b) timeout = 3000; if (cmd->opcode == SD_SWITCH_VOLTAGE) { err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); if (err < 0) goto out; clock_toggled = true; } rtsx_pci_init_cmd(pcr); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 0x40 | cmd_idx); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD1, 0xFF, (u8)(arg >> 24)); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD2, 0xFF, (u8)(arg >> 16)); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD3, 0xFF, (u8)(arg >> 8)); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD4, 0xFF, (u8)arg); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE); if (rsp_type == SD_RSP_TYPE_R2) { /* Read data from ping-pong buffer */ for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); stat_idx = 16; } else if (rsp_type != SD_RSP_TYPE_R0) { /* Read data from SD_CMDx registers */ for (i = SD_CMD0; i <= SD_CMD4; i++) rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); stat_idx = 5; } rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); err = rtsx_pci_send_cmd(pcr, timeout); if (err < 0) { sd_print_debug_regs(host); sd_clear_error(host); dev_dbg(sdmmc_dev(host), "rtsx_pci_send_cmd error (err = %d)\n", err); goto out; } if (rsp_type == SD_RSP_TYPE_R0) { err = 0; goto out; } /* Eliminate returned value of CHECK_REG_CMD */ ptr = rtsx_pci_get_cmd_data(pcr) + 1; /* Check (Start,Transmission) bit of Response */ if ((ptr[0] & 0xC0) != 0) { err = -EILSEQ; dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); goto out; } /* Check CRC7 */ if (!(rsp_type & SD_NO_CHECK_CRC7)) { if (ptr[stat_idx] & SD_CRC7_ERR) { err = -EILSEQ; dev_dbg(sdmmc_dev(host), "CRC7 error\n"); goto out; } } if (rsp_type == SD_RSP_TYPE_R2) { /* * The controller offloads the last byte {CRC-7, end bit 1'b1} * of response type R2. Assign dummy CRC, 0, and end bit to the * byte(ptr[16], goes into the LSB of resp[3] later). */ ptr[16] = 1; for (i = 0; i < 4; i++) { cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", i, cmd->resp[i]); } } else { cmd->resp[0] = get_unaligned_be32(ptr + 1); dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", cmd->resp[0]); } out: cmd->error = err; if (err && clock_toggled) rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); }
static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) { struct realtek_pci_sdmmc *host = mmc_priv(mmc); struct rtsx_pcr *pcr = host->pcr; struct mmc_command *cmd = mrq->cmd; struct mmc_data *data = mrq->data; unsigned int data_size = 0; if (host->eject) { cmd->error = -ENOMEDIUM; goto finish; } mutex_lock(&pcr->pcr_mutex); rtsx_pci_start_run(pcr); rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, host->initial_mode, host->double_clk, host->vpclk); rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); rtsx_pci_write_register(pcr, CARD_SHARE_MODE, CARD_SHARE_MASK, CARD_SHARE_48_SD); mutex_lock(&host->host_mutex); host->mrq = mrq; mutex_unlock(&host->host_mutex); if (mrq->data) data_size = data->blocks * data->blksz; if (!data_size || mmc_op_multi(cmd->opcode) || (cmd->opcode == MMC_READ_SINGLE_BLOCK) || (cmd->opcode == MMC_WRITE_BLOCK)) { sd_send_cmd_get_rsp(host, cmd); if (!cmd->error && data_size) { sd_rw_multi(host, mrq); if (mmc_op_multi(cmd->opcode) && mrq->stop) sd_send_cmd_get_rsp(host, mrq->stop); } } else { sd_normal_rw(host, mrq); } if (mrq->data) { if (cmd->error || data->error) data->bytes_xfered = 0; else data->bytes_xfered = data->blocks * data->blksz; } mutex_unlock(&pcr->pcr_mutex); finish: if (cmd->error) dev_dbg(sdmmc_dev(host), "cmd->error = %d\n", cmd->error); mutex_lock(&host->host_mutex); host->mrq = NULL; mutex_unlock(&host->host_mutex); mmc_request_done(mmc, mrq); }
static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) { struct timing_phase_path path[MAX_PHASE + 1]; int i, j, cont_path_cnt; int new_block, max_len, final_path_idx; u8 final_phase = 0xFF; /* Parse phase_map, take it as a bit-ring */ cont_path_cnt = 0; new_block = 1; j = 0; for (i = 0; i < MAX_PHASE + 1; i++) { if (phase_map & (1 << i)) { if (new_block) { new_block = 0; j = cont_path_cnt++; path[j].start = i; path[j].end = i; } else { path[j].end = i; } } else { new_block = 1; if (cont_path_cnt) { /* Calculate path length and middle point */ int idx = cont_path_cnt - 1; path[idx].len = path[idx].end - path[idx].start + 1; path[idx].mid = path[idx].start + path[idx].len / 2; } } } if (cont_path_cnt == 0) { dev_dbg(sdmmc_dev(host), "No continuous phase path\n"); goto finish; } else { /* Calculate last continuous path length and middle point */ int idx = cont_path_cnt - 1; path[idx].len = path[idx].end - path[idx].start + 1; path[idx].mid = path[idx].start + path[idx].len / 2; } /* Connect the first and last continuous paths if they are adjacent */ if (!path[0].start && (path[cont_path_cnt - 1].end == MAX_PHASE)) { /* Using negative index */ path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1; path[0].len += path[cont_path_cnt - 1].len; path[0].mid = path[0].start + path[0].len / 2; /* Convert negative middle point index to positive one */ if (path[0].mid < 0) path[0].mid += MAX_PHASE + 1; cont_path_cnt--; } /* Choose the longest continuous phase path */ max_len = 0; final_phase = 0; final_path_idx = 0; for (i = 0; i < cont_path_cnt; i++) { if (path[i].len > max_len) { max_len = path[i].len; final_phase = (u8)path[i].mid; final_path_idx = i; } dev_dbg(sdmmc_dev(host), "path[%d].start = %d\n", i, path[i].start); dev_dbg(sdmmc_dev(host), "path[%d].end = %d\n", i, path[i].end); dev_dbg(sdmmc_dev(host), "path[%d].len = %d\n", i, path[i].len); dev_dbg(sdmmc_dev(host), "path[%d].mid = %d\n", i, path[i].mid); } finish: dev_dbg(sdmmc_dev(host), "Final chosen phase: %d\n", final_phase); return final_phase; }