void __USER_TEXT sdram_init(void)
{
struct fmc_sdram_timing_cfg fs_timing_init;
struct fmc_sdram_cfg fs_init;
sdram_gpio_init();
RCC_AHB3PeriphClockCmd(RCC_AHB3ENR_FMCEN, 1);
fs_timing_init.lta_delay = 2; /* 2 clock cycles */
fs_timing_init.esr_delay = 7; /* 70ns */
fs_timing_init.sr_time = 4; /* 42ns */
fs_timing_init.rc_delay = 7; /* 70 */
fs_timing_init.wr_time = 2; /* 1+ 7ns */
fs_timing_init.rp_delay = 2; /* 20ns */
fs_timing_init.rcd_delay = 2; /* 20ns */
fs_init.bank = FMC_Bank2_SDRAM;
fs_init.column_bits_number = FMC_ColumnBits_Number_8b;
fs_init.row_bits_number = FMC_RowBits_Number_12b;
fs_init.sdmemory_data_width = SDRAM_MEMORY_WIDTH;
fs_init.internal_bank_number = FMC_InternalBank_Number_4;
fs_init.cas_latency = SDRAM_CAS_LATENCY;
fs_init.write_protection = FMC_Write_Protection_Disable;
fs_init.sd_clock_period = SDCLOCK_PERIOD;
fs_init.readburst = SDRAM_READBURST;
fs_init.readpipe_delay = FMC_ReadPipe_Delay_1;
fs_init.timing = &fs_timing_init;
fmc_sdram_config(&fs_init);
sdram_init_seq();
}
bool sdram_init()
{
/* SDRAM device configuration */
hsdram.Instance = FMC_SDRAM_DEVICE;
/* Timing configuration for 90 Mhz of SD clock frequency (180Mhz/2) */
/* TMRD: 2 Clock cycles */
SDRAM_Timing.LoadToActiveDelay = 2;
/* TXSR: min=70ns (6x11.90ns) */
SDRAM_Timing.ExitSelfRefreshDelay = 7;
/* TRAS: min=45ns (4x11.90ns) max=120k (ns) */
SDRAM_Timing.SelfRefreshTime = 7;
/* TRC: min=67ns (6x11.90ns) */
SDRAM_Timing.RowCycleDelay = 10;
/* TWR: 2 Clock cycles */
SDRAM_Timing.WriteRecoveryTime = 2;
/* TRP: 20ns => 2x11.90ns */
SDRAM_Timing.RPDelay = 3;
/* TRCD: 20ns => 2x11.90ns */
SDRAM_Timing.RCDDelay = 3;
hsdram.Init.SDBank = FMC_SDRAM_BANK1;
hsdram.Init.RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12;
hsdram.Init.ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_10;
hsdram.Init.MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_8;
hsdram.Init.InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4;
hsdram.Init.CASLatency = FMC_SDRAM_CAS_LATENCY_3;
hsdram.Init.WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE;
hsdram.Init.SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_3;
hsdram.Init.ReadBurst = FMC_SDRAM_RBURST_DISABLE;
hsdram.Init.ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_1;
/* Initialize the SDRAM controller */
if(HAL_SDRAM_Init(&hsdram, &SDRAM_Timing) != HAL_OK) {
return false;
}
sdram_init_seq(&hsdram, &command);
return true;
}