void process_flash_write(void){
WORD packet_length,i,c;
WORD block_remainder, packet_remainder;
if( !( EP2468STAT & 0x01 )){// EP2 FIFO NOT empty, host sent packet
FIFORESET = 0x80; SYNCDELAY;
packet_length = (EP2BCH << 8) | EP2BCL;
i = 0;
while(i < packet_length){
block_remainder = 256 - flash_addr_l;
packet_remainder = (packet_length > 256) ? 256 : packet_length;
c = min(block_remainder, packet_remainder);
if((flash_addr_m == 0) && (flash_addr_l == 0))
sector_erase(flash_addr_h);
page_write(flash_addr_h, flash_addr_m, flash_addr_l, &EP2FIFOBUF[i], c);
i += c;
// recalculate address
if((c + flash_addr_l) == 256){
flash_addr_l = 0x00;
if(flash_addr_m == 0xFF){
flash_addr_m = 0x00;
flash_addr_h += 1;
}
else
flash_addr_m += 1;
}
else
flash_addr_l += c;
}
FIFORESET = 0x00; SYNCDELAY;
OUTPKTEND = 0x82; // SKIP=1, do NOT pass buffer on to master
}
}
static int nor_erase(const struct spi_flash *flash, u32 offset, size_t len)
{
int sector_start = offset;
int sector_num = (u32)len / flash->sector_size;
while (sector_num) {
if (!sector_erase(sector_start)) {
sector_start += flash->sector_size;
sector_num--;
} else {
printk(BIOS_WARNING, "Erase failed at 0x%x!\n",
sector_start);
return -1;
}
}
return 0;
}
/*------------------------------------------------------*/
int PcLinkDecode (char *c)
{
/*
long i;
rtime t1,t2;
char cc[128];
double a,b,aa;
*/
switch(*c)
{
case '=':
LoadFromPc(++c);
break;
case ':':
puts_rld(++c);
return(eof);
case '*':
puts_C100(++c);
puts_C100("\r");
return(eof);
case '.':
GpsComm(++c);
return(eof);
case '@':
WriteSophie(++c);
return(eof);
case '-':
DeleteFromPc(++c);
break;
case '?':
ListToPc(++c);
break;
case '#':
SetAlarm();
break;
#ifndef WIN32
case '!':
sector_erase(SYSPAR,0);
SavePar(SYSPAR,0);
sector_erase(FONTS,0);
fonts=FONTS;
WriteGunData(Guns,&fonts);
fonts=SaveZone(SaveFonts(fonts));
break;
#endif
/* testiranje hitrosti
case 'r':
sscanf(++c,"%ld,%lf",&i,&a);
ReadTime(&t1);
watchdog();
PIT_disable();
while(i--)
b=sqrt(a);
PIT_enable();
wait(5);
ReadTime(&t2);
sprintf(cc,">>> %lf\r\n",dtime(&t2,&t1));
puts_pc(cc);
beep(100);
break;
case 'm':
sscanf(++c,"%ld,%lf,&lf",&i,&a,&b);
ReadTime(&t1);
watchdog();
PIT_disable();
while(i--)
aa=a*b;
PIT_enable();
wait(5);
ReadTime(&t2);
sprintf(cc,">>> %lf\r\n",dtime(&t2,&t1));
puts_pc(cc);
beep(100);
break;
case 'p':
sscanf(++c,"%ld,%lf,&lf",&i,&a,&b);
ReadTime(&t1);
watchdog();
PIT_disable();
while(i--)
aa=pow(a,b);
PIT_enable();
wait(5);
ReadTime(&t2);
sprintf(cc,">>> %lf\r\n",dtime(&t2,&t1));
puts_pc(cc);
beep(100);
break;
case 'e':
sscanf(++c,"%ld,%lf",&i,&a);
ReadTime(&t1);
watchdog();
PIT_disable();
while(i--)
aa=exp(a);
PIT_enable();
wait(5);
ReadTime(&t2);
sprintf(cc,">>> %lf\r\n",dtime(&t2,&t1));
puts_pc(cc);
beep(100);
break;
case 's':
sscanf(++c,"%ld,%lf",&i,&a);
ReadTime(&t1);
watchdog();
PIT_disable();
while(i--)
aa=sin(a);
PIT_enable();
wait(5);
ReadTime(&t2);
sprintf(cc,">>> %lf\r\n",dtime(&t2,&t1));
puts_pc(cc);
beep(100);
break;
case 't':
sscanf(++c,"%ld,%lf",&i,&a);
ReadTime(&t1);
watchdog();
PIT_disable();
while(i--)
aa=tan(a);
PIT_enable();
wait(5);
ReadTime(&t2);
sprintf(cc,">>> %lf\r\n",dtime(&t2,&t1));
puts_pc(cc);
beep(100);
break;
case 'a':
sscanf(++c,"%ld,%lf",&i,&a);
ReadTime(&t1);
watchdog();
PIT_disable();
while(i--)
aa=atan(a);
PIT_enable();
wait(5);
ReadTime(&t2);
sprintf(cc,">>> %lf\r\n",dtime(&t2,&t1));
puts_pc(cc);
beep(100);
break;
*/
default:
if(chrtx(c))
Ungetch(chrtx(c),0);
break;
}
return(null);
}
/*******************************************************************************
* Pull EP1 data
*******************************************************************************/
void ep1_pool(void){
BYTE i;
WORD adr;
BYTE new_data = 0;
// Test data for internal test
if(FPGA_INT0 && FPGA_DONE && !prev_done && !cmd_cnt){
EP8FIFOCFG = 0x00; SYNCDELAY;
FIFORESET = 0x08; SYNCDELAY;
FIFORESET = 0x00; SYNCDELAY;
EP8FIFOBUF[0] = 0x12;
EP8FIFOBUF[1] = 0x34;
EP8FIFOBUF[2] = 0x56;
EP8FIFOBUF[3] = 0x78;
EP8FIFOBUF[4] = 0x90;
EP8FIFOBUF[5] = 0xAB;
EP8FIFOBUF[6] = 0xCD;
EP8FIFOBUF[7] = 0xEF;
EP8BCH = 0;
EP8BCL = 8;
EP8FIFOCFG = 0x10; SYNCDELAY;
prev_done = 1;
}
if( !( EP1OUTCS & 0x02) ){ // Got something
cmd_cnt++;
for (i = 0; i < 0x40; i++)
EP1INBUF[i] = 0xFF; // fill output buffer
switch(EP1OUTBUF[0]){ // Decode command
//-----------------------------------------------------------------
default:
case CMD_READ_VERSION:
EP1INBUF[0] = fx2_ver_maj_;
EP1INBUF[1] = fx2_ver_min_;
EP1INBUF[2] = fx2_tip_maj_;
EP1INBUF[3] = fx2_tip_min_;
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_SET_AUTORESPONSE:
sts_int_auto_configured = 1;
iar_adress = EP1OUTBUF[1];
iar_count = EP1OUTBUF[2];
iar_int_idx = 0;
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_GET_AUTORESPONSE:
EP1INBUF[0] = iar_int_idx;
for(i = 0; i < 32; i++)
EP1INBUF[i+1] = auto_response_data[i];
iar_int_idx = 0;
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_SWITCH_MODE:
sts_current_mode = 1;
new_data = 1;
EP1INBUF[0] = EP1OUTBUF[1];
break;
//-----------------------------------------------------------------
case CMD_READ_STATUS:
sts_flash_busy = get_flash_busy();
sts_booting = FPGA_DONE;
sts_fpga_prog = 0xaa;
sts_high_speed_mode = (USBCS & bmHSM) ? 1 : 255;
new_data = 1;
EP1INBUF[0] = sts_fifo_error;
EP1INBUF[1] = sts_current_mode;
EP1INBUF[2] = sts_flash_busy;
EP1INBUF[3] = sts_fpga_prog;
EP1INBUF[4] = sts_booting;
EP1INBUF[5] = sts_i2c_new_data;
EP1INBUF[6] = sts_int_auto_configured;
EP1INBUF[7] = sts_high_speed_mode;
sts_i2c_new_data = 0;
break;
//-----------------------------------------------------------------
case CMD_RESET_FIFO_STATUS:
sts_fifo_error = 0;
FIFORESET = 0x80; SYNCDELAY; // NAK all requests from host.
switch(EP1OUTBUF[1]){
case 2:
EP2FIFOCFG = 0x48; SYNCDELAY;
FIFORESET = 0x02; SYNCDELAY;
break;
case 4:
EP4FIFOCFG = 0x48; SYNCDELAY;
FIFORESET = 0x04; SYNCDELAY;
break;
case 6:
EP6FIFOCFG = 0x48; SYNCDELAY;
FIFORESET = 0x06; SYNCDELAY;
break;
default: // 0
EP2FIFOCFG = 0x48; SYNCDELAY;
EP4FIFOCFG = 0x48; SYNCDELAY;
EP6FIFOCFG = 0x48; SYNCDELAY;
EP8FIFOCFG = 0x10; SYNCDELAY;
FIFORESET = 0x02; SYNCDELAY;
FIFORESET = 0x04; SYNCDELAY;
FIFORESET = 0x06; SYNCDELAY;
}
FIFORESET = 0x00; SYNCDELAY; // Resume normal operation.
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_FLASH_WRITE:
if (EP1OUTBUF[4] > 59) EP1OUTBUF[4] = 59;
page_write(EP1OUTBUF[1], EP1OUTBUF[2], EP1OUTBUF[3], &EP1OUTBUF[5], EP1OUTBUF[4]); //highest, high, low adr, read_ptr, size
//-----------------------------------------------------------------
case CMD_FLASH_READ:
if (EP1OUTBUF[4] > 64) EP1OUTBUF[4] = 64;
page_read(EP1OUTBUF[1], EP1OUTBUF[2], EP1OUTBUF[3], &EP1INBUF[0], EP1OUTBUF[4]); //highest, high, low adr, read_ptr, size
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_FLASH_ERASE:
// busy_polling();
// On some modules it cause API error - better to do it from software side
bulk_erase();
new_data = 1;
sts_flash_busy = 1;
break;
//-----------------------------------------------------------------
case CMD_SECTOR_ERASE:
sector_erase(EP1OUTBUF[1]);
new_data = 1;
sts_flash_busy = 1;
break;
//-----------------------------------------------------------------
case CMD_FLASH_WRITE_COMMAND:
EP1INBUF[0] = 0x55;
spi_command(EP1OUTBUF[1], &EP1OUTBUF[3], EP1OUTBUF[2], &EP1INBUF[1]);
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_EEPROM_WRITE:
adr = EP1OUTBUF[1];
adr = (adr << 8) + EP1OUTBUF[2];
if (EP1OUTBUF[3] > 32) EP1OUTBUF[3] = 32;
EEPROMWrite(adr, EP1OUTBUF[3], &EP1OUTBUF[4]); // adress, size, data
//-----------------------------------------------------------------
case CMD_EEPROM_READ:
adr = EP1OUTBUF[1];
adr = (adr << 8) + EP1OUTBUF[2];
EEPROMRead(adr, EP1OUTBUF[3], &EP1INBUF[0]); // adress, size, data
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_GET_FIFO_STATUS:
EP1INBUF[0] = EP2CS;
EP1INBUF[1] = EP4CS;
EP1INBUF[2] = EP6CS;
EP1INBUF[3] = EP8CS;
EP1INBUF[4] = EP2FIFOBCH;
EP1INBUF[5] = EP4FIFOBCH;
EP1INBUF[6] = EP6FIFOBCH;
EP1INBUF[7] = EP8FIFOBCH;
EP1INBUF[8] = EP2FIFOBCL;
EP1INBUF[9] = EP4FIFOBCL;
EP1INBUF[10] = EP6FIFOBCL;
EP1INBUF[11] = EP8FIFOBCL;
EP1INBUF[12] = EP2FIFOFLGS;
EP1INBUF[13] = EP4FIFOFLGS;
EP1INBUF[14] = EP6FIFOFLGS;
EP1INBUF[15] = EP8FIFOFLGS;
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_I2C_WRITE:
I2CWrite(EP1OUTBUF[1], EP1OUTBUF[2], &EP1OUTBUF[3]); // adress, size, data
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_I2C_READ:
I2CRead(EP1OUTBUF[1], EP1OUTBUF[2], &EP1INBUF[0]); // adress, size, data
new_data = 1;
break;
//-----------------------------------------------------------------
/*
case CMD_I2C_WRITE_READ:
i = EP1OUTBUF[1];
I2CWrite(i, EP1OUTBUF[2], &EP1OUTBUF[4]); // adress, size, data
delaycnt = 0;
while (INT0_PIN == 0){
EZUSB_Delay1ms();
delaycnt++;
if (delaycnt > 800)
break;
continue;
}
I2CRead(i, EP1OUTBUF[3], &EP1INBUF[0]); // adress, size, data
new_data = 1;
break;
*/
//-----------------------------------------------------------------
case CMD_FPGA_POWER:
if (EP1OUTBUF[1] == 0){
FPGA_POWER = 0;
sts_int_auto_configured = 0;
}
else{
IOD = 0x03; // Enable Power and disable Reset
OED = 0x03; // PROG_B and POWER
FPGA_POWER = 1;
}
EP1INBUF[0] = (FPGA_POWER) ? 1 : 0;
EP1INBUF[1] = 0xAA;
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_FPGA_RESET:
FPGA_INT1 = (EP1OUTBUF[1]) ? 1 : 0;
EP1INBUF[0] = FPGA_INT1;
EP1INBUF[1] = 0xAA;
new_data = 1;
break;
//-----------------------------------------------------------------
case CMD_DEV_LOCK:
if(EP1OUTBUF[1] == 0x01){ // Driver trying to lock device
if(lock == 0){ // Device is free
EP1INBUF[0] = 0x22; // Sucessfull lock
lock = 1;
}
else // Device is locked
EP1INBUF[0] = 0x00; // Already locked
}
else{ // Driver trying to unlock device
if(lock == 1){ // Device is locked
EP1INBUF[0] = 0x33; // Sucessfull unlock
lock = 0;
}
else // Device is unlocked
EP1INBUF[0] = 0x00; // Got problem
}
new_data = 1;
break;
//-----------------------------------------------------------------
}
EP1OUTBC = EP1DATA_COUNT; // Free input buffer
}
if(new_data){ // Have something to send
if ( !(EP1INCS & 0x02)){ // Can send ?
EP1INBC = EP1DATA_COUNT; // Send
new_data = 0;
}
}
}
static int
program_flash(Environ *e, Self *s, int offset, uByte *data, int len)
{
Flash *flash = s->type;
int i;
uByte *buf = 0;
int buflen = 0;
uByte *bp;
int bpoff;
int bpsize;
Bool diag = diagnostic_mode(e);
int width = s->width;
int partswide = s->partswide;
const Sector *sectors = flash->sectors;
int mask = width - 1;
if (offset < 0)
return 0;
DPRINTF(("program_flash: e %p, s %p, offset %#x, data %p, len %d\n",
e, s, offset, data, len));
while (len)
{
int sector;
int soffset;
int ssize;
int off;
int sz;
int diffs;
for (i = 1; sectors[i].size; i++)
if (sectors[i].start * partswide > offset)
break;
sector = i - 1;
soffset = sectors[sector].start * partswide;
ssize = sectors[sector].size * partswide;
DPRINTF(("program_flash: sector %d, offset %#x, size %d\n",
sector, soffset, ssize));
/* check for write past end of flash */
if (soffset + ssize <= offset)
{
if (buf)
free(buf);
return 0;
}
off = offset - soffset;
sz = len < (ssize - off) ? len : (ssize - off);
DPRINTF(("program_flash: off %#x, sz %d\n", off, sz));
if (sz < 0 || sz > ssize)
{
cprintf(e, "sz out of range, %d\n", sz);
if (buf)
free(buf);
return 0;
}
/* check to see if we need to erase or program*/
diffs = compare_flash(e, s, offset, data, sz, 0);
DPRINTF(("program_flash: compare, %#x, %d, %d\n", offset, sz, diffs));
if (diffs & 2)
{
diffs = 1;
if (off || sz < ssize)
{
/* preserve the sector contents */
if (buflen < ssize)
{
if (buf)
free(buf);
buf = (uByte *)malloc(ssize);
buflen = ssize;
if (!buf)
{
cprintf(e, "Unable to allocate sector buffer\n");
return 0;
}
DPRINTF(("buf = %p\n", buf));
}
for (i = 0; i < ssize; i += width)
read_word(e, s, soffset + i, &buf[i]);
for (i = 0; i < sz; i++)
buf[off + i] = data[i];
bp = buf;
}
else
bp = data;
bpoff = soffset;
bpsize = ssize;
DPRINTF(("program_flash: bp %p, bpoff %#x, bpsize %d\n",
bp, bpoff, bpsize));
/* erase sector */
if (diag)
cprintf(e, "Erasing sector %d\n", sector);
else
spin_cursor(e);
DPRINTF(("program_flash: erasing sector %#x\n", soffset));
sector_erase(e, s, soffset);
}
else
{
bp = data;
bpoff = offset;
bpsize = sz;
DPRINTF(("program_flash: 2 bp %p, bpoff %#x, bpsize %d\n",
bp, bpoff, bpsize));
}
if (diffs & 1)
{
if (diag)
cprintf(e, "Programming sector %d\n", sector);
else
spin_cursor(e);
DPRINTF(("program_flash: programming offset %#x, size %d\n", bpoff, bpsize));
/* program */
if (bpoff & mask)
{
/* handle odd bytes */
int n = width - (bpoff & mask);
if (n > bpsize)
n = bpsize;
DPRINTF(("program_flash: %d misaligned bytes at %#x\n", n, bpoff, bp));
read_word(e, s, bpoff & ~mask, s->buf);
for (i = 0; i < n; i++)
s->buf[(bpoff & mask) + i] = bp[i];
program_word(e, s, bpoff & ~mask, s->buf);
}
else
i = 0;
for (; i + width - 1 < bpsize; i += width)
{
if ((((i / width) + 1) % (4*1024)) == 0)
spin_cursor(e);
program_word(e, s, (bpoff + i) & ~mask, &bp[i]);
}
DPRINTF(("program_flash: %d aligned bytes remainder at %#x, %p\n", i, bpoff, bp));
if (i < bpsize)
{
/* handle odd bytes at the tail */
int j;
DPRINTF(("program_flash: %d misaligned bytes remainder at %#x, %p\n", bpsize - i, bpoff + i, bp + i));
read_word(e, s, (bpoff + i) & ~mask, s->buf);
DPRINTF(("program_flash: buf[0] %#x, buf[1] %#x\n", s->buf[0], s->buf[1]));
for (j = 0; i < bpsize; j++, i++)
s->buf[j] = bp[i];
DPRINTF(("program_flash: new buf[0] %#x, buf[1] %#x\n", s->buf[0], s->buf[1]));
program_word(e, s, (bpoff + i) & ~mask, s->buf);
}
/* verify bytes */
diffs = compare_flash(e, s, bpoff, bp, bpsize, 1);
DPRINTF(("program_flash: compare: bpoff %p, bp %#x, bpsize %d, diffs %d\n",
bpoff, bp, bpsize, diffs));
}
offset += sz;
data += sz;
len -= sz;
}
if (buf)
free(buf);
DPRINTF(("buf = %p free\n", buf));
DPRINTF(("program_flash: offset %#x, data %#x, len %d\n",
offset, data, len));
/* return OK */
return 1;
}
