static void serial_omap_stop_tx(struct uart_port *port) { struct uart_omap_port *up = (struct uart_omap_port *)port; if (up->use_dma && up->uart_dma.tx_dma_channel != OMAP_UART_DMA_CH_FREE) { /* * Check if dma is still active. If yes do nothing, * return. Else stop dma */ if (omap_get_dma_active_status(up->uart_dma.tx_dma_channel)) return; omap_stop_dma(up->uart_dma.tx_dma_channel); omap_free_dma(up->uart_dma.tx_dma_channel); up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; serial_omap_port_disable(up); } serial_omap_port_enable(up); if (up->ier & UART_IER_THRI) { up->ier &= ~UART_IER_THRI; serial_out(up, UART_IER, up->ier); } serial_omap_port_disable(up); }
static void serial_omap_pm(struct uart_port *port, unsigned int state, unsigned int oldstate) { struct uart_omap_port *up = (struct uart_omap_port *)port; unsigned char efr; unsigned char lcr; dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->pdev->id); serial_omap_port_enable(up); lcr = serial_in(up, UART_LCR); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); efr = serial_in(up, UART_EFR); serial_out(up, UART_EFR, efr | UART_EFR_ECB); serial_out(up, UART_LCR, 0); serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_EFR, efr); serial_out(up, UART_LCR, lcr); if (state) pm_runtime_put_sync(&up->pdev->dev); else serial_omap_port_disable(up); }
static int serial_omap_start_rxdma(struct uart_omap_port *up) { int ret = 0; if (up->uart_dma.rx_dma_channel == -1) { serial_omap_port_enable(up); ret = omap_request_dma(up->uart_dma.uart_dma_rx, "UART Rx DMA", (void *)uart_rx_dma_callback, up, &(up->uart_dma.rx_dma_channel)); if (ret < 0) return ret; omap_set_dma_src_params(up->uart_dma.rx_dma_channel, 0, OMAP_DMA_AMODE_CONSTANT, up->uart_dma.uart_base, 0, 0); omap_set_dma_dest_params(up->uart_dma.rx_dma_channel, 0, OMAP_DMA_AMODE_POST_INC, up->uart_dma.rx_buf_dma_phys, 0, 0); omap_set_dma_transfer_params(up->uart_dma.rx_dma_channel, OMAP_DMA_DATA_TYPE_S8, up->uart_dma.rx_buf_size, 1, OMAP_DMA_SYNC_ELEMENT, up->uart_dma.uart_dma_rx, 0); } up->uart_dma.prev_rx_dma_pos = up->uart_dma.rx_buf_dma_phys; /* FIXME: Cache maintenance needed here? */ omap_start_dma(up->uart_dma.rx_dma_channel); mod_timer(&up->uart_dma.rx_timer, jiffies + usecs_to_jiffies(up->uart_dma.rx_poll_rate)); up->uart_dma.rx_dma_used = true; return ret; }
static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch) { struct uart_omap_port *up = (struct uart_omap_port *)port; serial_omap_port_enable(up); wait_for_xmitr(up); serial_out(up, UART_TX, ch); serial_omap_port_disable(up); }
static void serial_omap_enable_ms(struct uart_port *port) { struct uart_omap_port *up = (struct uart_omap_port *)port; dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->pdev->id); serial_omap_port_enable(up); up->ier |= UART_IER_MSI; serial_out(up, UART_IER, up->ier); serial_omap_port_disable(up); }
static void serial_omap_stop_rx(struct uart_port *port) { struct uart_omap_port *up = (struct uart_omap_port *)port; serial_omap_port_enable(up); if (up->use_dma) serial_omap_stop_rxdma(up); up->ier &= ~UART_IER_RLSI; up->port.read_status_mask &= ~UART_LSR_DR; serial_out(up, UART_IER, up->ier); serial_omap_port_disable(up); }
int omap_uart_wake(u8 uart_num) { if (uart_num > OMAP_MAX_HSUART_PORTS) return -ENODEV; if (!ui[uart_num - 1]) return -ENODEV; serial_omap_port_enable(ui[uart_num - 1]); serial_omap_port_disable(ui[uart_num - 1]); return 0; }
static int serial_omap_poll_get_char(struct uart_port *port) { struct uart_omap_port *up = (struct uart_omap_port *)port; unsigned int status; serial_omap_port_enable(up); status = serial_in(up, UART_LSR); if (!(status & UART_LSR_DR)) return NO_POLL_CHAR; status = serial_in(up, UART_RX); serial_omap_port_disable(up); return status; }
/* Used by ext client device connected to uart to control uart */ int omap_serial_ext_uart_enable(u8 port_id) { struct uart_omap_port *up; int err = 0; if (port_id > OMAP_MAX_HSUART_PORTS) { pr_err("Invalid Port_id %d passed to %s\n", port_id, __func__); err = -ENODEV; } else { up = ui[port_id]; serial_omap_port_enable(up); } return err; }
//static unsigned int serial_omap_tx_empty(struct uart_port *port) unsigned int serial_omap_tx_empty(struct uart_port *port) { struct uart_omap_port *up = (struct uart_omap_port *)port; unsigned long flags = 0; unsigned int ret = 0; serial_omap_port_enable(up); dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->pdev->id); spin_lock_irqsave(&up->port.lock, flags); ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0; spin_unlock_irqrestore(&up->port.lock, flags); serial_omap_port_disable(up); return ret; }
/** * serial_omap_irq() - This handles the interrupt from one port * @irq: uart port irq number * @dev_id: uart port info */ static inline irqreturn_t serial_omap_irq(int irq, void *dev_id) { struct uart_omap_port *up = dev_id; unsigned int iir, lsr; unsigned int int_id; unsigned long flags; int ret = IRQ_HANDLED; u8 tx_fifo_lvl; serial_omap_port_enable(up); iir = serial_in(up, UART_IIR); if (iir & UART_IIR_NO_INT) { serial_omap_port_disable(up); return IRQ_NONE; } int_id = iir & UART_OMAP_IIR_ID; spin_lock_irqsave(&up->port.lock, flags); lsr = serial_in(up, UART_LSR); if (int_id == UART_IIR_RDI || int_id == UART_OMAP_IIR_RX_TIMEOUT || int_id == UART_IIR_RLSI) { if (!up->use_dma) { if (lsr & UART_LSR_DR) receive_chars(up, &lsr); } else { up->ier &= ~(UART_IER_RDI | UART_IER_RLSI); serial_out(up, UART_IER, up->ier); if ((serial_omap_start_rxdma(up) != 0) && (lsr & UART_LSR_DR)) receive_chars(up, &lsr); } } check_modem_status(up); if (int_id == UART_IIR_THRI) { tx_fifo_lvl = serial_in(up, UART_OMAP_TXFIFO_LVL); if (lsr & UART_LSR_THRE || tx_fifo_lvl < up->port.fifosize) transmit_chars(up, tx_fifo_lvl); else ret = IRQ_NONE; } spin_unlock_irqrestore(&up->port.lock, flags); serial_omap_port_disable(up); up->port_activity = jiffies; return ret; }
static void serial_omap_break_ctl(struct uart_port *port, int break_state) { struct uart_omap_port *up = (struct uart_omap_port *)port; unsigned long flags = 0; dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->pdev->id); serial_omap_port_enable(up); spin_lock_irqsave(&up->port.lock, flags); if (break_state == -1) up->lcr |= UART_LCR_SBC; else up->lcr &= ~UART_LCR_SBC; serial_out(up, UART_LCR, up->lcr); spin_unlock_irqrestore(&up->port.lock, flags); serial_omap_port_disable(up); }
static void serial_omap_shutdown(struct uart_port *port) { struct uart_omap_port *up = (struct uart_omap_port *)port; unsigned long flags = 0; dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->pdev->id); serial_omap_port_enable(up); /* * Disable interrupts & wakeup events from this port */ up->ier = 0; up->wer_restore = 0; serial_out(up, UART_OMAP_WER, 0); serial_out(up, UART_IER, 0); spin_lock_irqsave(&up->port.lock, flags); up->port.mctrl &= ~TIOCM_OUT2; serial_omap_set_mctrl(&up->port, up->port.mctrl); spin_unlock_irqrestore(&up->port.lock, flags); /* * Disable break condition and FIFOs */ serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC); serial_omap_clear_fifos(up); /* * Read data port to reset things, and then free the irq */ if (serial_in(up, UART_LSR) & UART_LSR_DR) (void) serial_in(up, UART_RX); if (up->use_dma) { dma_free_coherent(up->port.dev, UART_XMIT_SIZE, up->port.state->xmit.buf, up->uart_dma.tx_buf_dma_phys); up->port.state->xmit.buf = NULL; serial_omap_stop_rx(port); dma_free_coherent(up->port.dev, up->uart_dma.rx_buf_size, up->uart_dma.rx_buf, up->uart_dma.rx_buf_dma_phys); up->uart_dma.rx_buf = NULL; } serial_omap_port_disable(up); free_irq(up->port.irq, up); }
static int serial_omap_resume(struct device *dev) { struct uart_omap_port *up = dev_get_drvdata(dev); if (up) { uart_resume_port(&serial_omap_reg, &up->port); up->suspended = false; serial_omap_port_enable(up);//add enable and disable to make sure RTS state right after resume if (up->rts_mux_driver_control && up->rts_pullup_in_suspend) { omap_rts_mux_write(0, up->port.line); up->rts_pullup_in_suspend = 0; } serial_omap_port_disable(up); } return 0; }
/* TBD: Should be removed once we irq-chaining mechanism in place */ u32 omap_uart_resume_idle() { int i; u32 ret = 0; for (i = 0; i < OMAP_MAX_HSUART_PORTS; i++) { struct uart_omap_port *up = ui[i]; if (!up) continue; if (up->chk_wakeup(up->pdev)) { serial_omap_port_enable(up); serial_omap_port_disable(up); ret++; } } return ret; }
static unsigned int serial_omap_get_mctrl(struct uart_port *port) { struct uart_omap_port *up = (struct uart_omap_port *)port; unsigned char status; unsigned int ret = 0; serial_omap_port_enable(up); status = check_modem_status(up); serial_omap_port_disable(up); dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->pdev->id); if (status & UART_MSR_DCD) ret |= TIOCM_CAR; if (status & UART_MSR_RI) ret |= TIOCM_RNG; if (status & UART_MSR_DSR) ret |= TIOCM_DSR; if (status & UART_MSR_CTS) ret |= TIOCM_CTS; return ret; }
//static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl) { struct uart_omap_port *up = (struct uart_omap_port *)port; unsigned char mcr = 0; dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->pdev->id); if (mctrl & TIOCM_RTS) mcr |= UART_MCR_RTS; if (mctrl & TIOCM_DTR) mcr |= UART_MCR_DTR; if (mctrl & TIOCM_OUT1) mcr |= UART_MCR_OUT1; if (mctrl & TIOCM_OUT2) mcr |= UART_MCR_OUT2; if (mctrl & TIOCM_LOOP) mcr |= UART_MCR_LOOP; serial_omap_port_enable(up); up->mcr = serial_in(up, UART_MCR); up->mcr |= mcr; serial_out(up, UART_MCR, up->mcr); serial_omap_port_disable(up); }
static void serial_omap_set_termios(struct uart_port *port, struct ktermios *termios, struct ktermios *old) { struct uart_omap_port *up = (struct uart_omap_port *)port; unsigned char cval = 0; unsigned long flags = 0; unsigned int baud, quot; switch (termios->c_cflag & CSIZE) { case CS5: cval = UART_LCR_WLEN5; break; case CS6: cval = UART_LCR_WLEN6; break; case CS7: cval = UART_LCR_WLEN7; break; default: case CS8: cval = UART_LCR_WLEN8; break; } if (termios->c_cflag & CSTOPB) cval |= UART_LCR_STOP; if (termios->c_cflag & PARENB) cval |= UART_LCR_PARITY; if (!(termios->c_cflag & PARODD)) cval |= UART_LCR_EPAR; /* * Ask the core to calculate the divisor for us. */ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13); quot = serial_omap_get_divisor(port, baud); up->dll = quot & 0xff; up->dlh = quot >> 8; up->mdr1 = UART_OMAP_MDR1_DISABLE; up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 | UART_FCR_ENABLE_FIFO; if (up->use_dma) up->fcr |= UART_FCR_DMA_SELECT; /* * Ok, we're now changing the port state. Do it with * interrupts disabled. */ serial_omap_port_enable(up); spin_lock_irqsave(&up->port.lock, flags); /* * Update the per-port timeout. */ uart_update_timeout(port, termios->c_cflag, baud); up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; if (termios->c_iflag & INPCK) up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE; if (termios->c_iflag & (BRKINT | PARMRK)) up->port.read_status_mask |= UART_LSR_BI; /* * Characters to ignore */ up->port.ignore_status_mask = 0; if (termios->c_iflag & IGNPAR) up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; if (termios->c_iflag & IGNBRK) { up->port.ignore_status_mask |= UART_LSR_BI; /* * If we're ignoring parity and break indicators, * ignore overruns too (for real raw support). */ if (termios->c_iflag & IGNPAR) up->port.ignore_status_mask |= UART_LSR_OE; } /* * ignore all characters if CREAD is not set */ if ((termios->c_cflag & CREAD) == 0) up->port.ignore_status_mask |= UART_LSR_DR; /* * Modem status interrupts */ up->ier &= ~UART_IER_MSI; if (UART_ENABLE_MS(&up->port, termios->c_cflag)) up->ier |= UART_IER_MSI; serial_out(up, UART_IER, up->ier); serial_out(up, UART_LCR, cval); /* reset DLAB */ up->lcr = cval; up->scr = OMAP_UART_SCR_TX_EMPTY; /* FIFOs and DMA Settings */ /* FCR can be changed only when the * baud clock is not running * DLL_REG and DLH_REG set to 0. */ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_out(up, UART_DLL, 0); serial_out(up, UART_DLM, 0); serial_out(up, UART_LCR, 0); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); up->efr = serial_in(up, UART_EFR); serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); up->mcr = serial_in(up, UART_MCR); serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); /* FIFO ENABLE, DMA MODE */ serial_out(up, UART_FCR, up->fcr); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); if (up->use_dma) { if (up->errata & OMAP4_UART_ERRATA_i659_TX_THR) { serial_out(up, UART_MDR3, SET_DMA_TX_THRESHOLD); serial_out(up, UART_TX_DMA_THRESHOLD, TX_FIFO_THR_LVL); } serial_out(up, UART_TI752_TLR, 0); up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8); } serial_out(up, UART_OMAP_SCR, up->scr); serial_out(up, UART_EFR, up->efr); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); serial_out(up, UART_MCR, up->mcr); /* Protocol, Baud Rate, and Interrupt Settings */ if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) omap_uart_mdr1_errataset(up, up->mdr1); else serial_out(up, UART_OMAP_MDR1, up->mdr1); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); up->efr = serial_in(up, UART_EFR); serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); serial_out(up, UART_LCR, 0); serial_out(up, UART_IER, 0); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_DLL, up->dll); /* LS of divisor */ serial_out(up, UART_DLM, up->dlh); /* MS of divisor */ serial_out(up, UART_LCR, 0); serial_out(up, UART_IER, up->ier); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); serial_out(up, UART_EFR, up->efr); serial_out(up, UART_LCR, cval); if (baud > 230400 && baud != 3000000) up->mdr1 = UART_OMAP_MDR1_13X_MODE; else up->mdr1 = UART_OMAP_MDR1_16X_MODE; if (up->errata & UART_ERRATA_i202_MDR1_ACCESS) omap_uart_mdr1_errataset(up, up->mdr1); else serial_out(up, UART_OMAP_MDR1, up->mdr1); /* Hardware Flow Control Configuration */ if (termios->c_cflag & CRTSCTS) { serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); up->mcr = serial_in(up, UART_MCR); serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR); serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); up->efr = serial_in(up, UART_EFR); serial_out(up, UART_EFR, up->efr | UART_EFR_ECB); serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG); up->efr |= (UART_EFR_CTS | UART_EFR_RTS); serial_out(up, UART_EFR, up->efr); /* Enable AUTORTS and AUTOCTS */ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); up->mcr |= UART_MCR_RTS; serial_out(up, UART_MCR, up->mcr); serial_out(up, UART_LCR, cval); } else { serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); up->efr = serial_in(up, UART_EFR); up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS); serial_out(up, UART_EFR, up->efr); /* Disable AUTORTS and AUTOCTS */ serial_out(up, UART_LCR, cval); } serial_omap_set_mctrl(&up->port, up->port.mctrl); /* Software Flow Control Configuration */ serial_omap_configure_xonxoff(up, termios); /* Now we are ready for RX data: enable rts line */ #if 0 if (up->rts_mux_driver_control && up->rts_pullup_in_suspend) { omap_rts_mux_write(0, up->port.line); up->rts_pullup_in_suspend = 0; } #endif spin_unlock_irqrestore(&up->port.lock, flags); serial_omap_port_disable(up); dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->pdev->id); }
static int serial_omap_startup(struct uart_port *port) { struct uart_omap_port *up = (struct uart_omap_port *)port; unsigned long flags = 0; int retval; /* * Allocate the IRQ */ retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags, up->name, up); if (retval) return retval; dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->pdev->id); serial_omap_port_enable(up); /* * Clear the FIFO buffers and disable them. * (they will be reenabled in set_termios()) */ serial_omap_clear_fifos(up); /* For Hardware flow control */ serial_out(up, UART_MCR, UART_MCR_RTS); up->mcr = serial_in(up, UART_MCR); /* * Clear the interrupt registers. */ (void) serial_in(up, UART_LSR); if (serial_in(up, UART_LSR) & UART_LSR_DR) (void) serial_in(up, UART_RX); (void) serial_in(up, UART_IIR); //(void) serial_in(up, UART_MSR); //CTS status change before startup will be missed, no need to clear /* * Now, initialize the UART */ serial_out(up, UART_LCR, UART_LCR_WLEN8); spin_lock_irqsave(&up->port.lock, flags); /* * Most PC uarts need OUT2 raised to enable interrupts. */ up->port.mctrl |= TIOCM_OUT2; serial_omap_set_mctrl(&up->port, up->port.mctrl); spin_unlock_irqrestore(&up->port.lock, flags); up->msr_saved_flags = 0; if (up->use_dma) { free_page((unsigned long)up->port.state->xmit.buf); up->port.state->xmit.buf = dma_alloc_coherent(NULL, UART_XMIT_SIZE, (dma_addr_t *)&(up->uart_dma.tx_buf_dma_phys), 0); init_timer(&(up->uart_dma.rx_timer)); up->uart_dma.rx_timer.function = serial_omap_rxdma_poll; up->uart_dma.rx_timer.data = up->pdev->id; /* Currently the buffer size is 4KB. Can increase it */ up->uart_dma.rx_buf = dma_alloc_coherent(NULL, up->uart_dma.rx_buf_size, (dma_addr_t *)&(up->uart_dma.rx_buf_dma_phys), 0); } /* * Finally, enable interrupts. Note: Modem status interrupts * are set via set_termios(), which will be occurring imminently * anyway, so we don't enable them here. */ up->ier = UART_IER_RLSI | UART_IER_RDI; serial_out(up, UART_IER, up->ier); /* Enable module level wake up */ up->wer_restore = up->wer; serial_out(up, UART_OMAP_WER, up->wer); serial_omap_port_disable(up); up->port_activity = jiffies; return 0; }
static void serial_omap_start_tx(struct uart_port *port) { struct uart_omap_port *up = (struct uart_omap_port *)port; struct circ_buf *xmit; unsigned int start; int ret = 0; if (!up->use_dma) { serial_omap_port_enable(up); serial_omap_enable_ier_thri(up); serial_omap_port_disable(up); return; } if (up->uart_dma.tx_dma_used) return; xmit = &up->port.state->xmit; if (up->uart_dma.tx_dma_channel == OMAP_UART_DMA_CH_FREE) { serial_omap_port_enable(up); ret = omap_request_dma(up->uart_dma.uart_dma_tx, "UART Tx DMA", (void *)uart_tx_dma_callback, up, &(up->uart_dma.tx_dma_channel)); if (ret < 0) { serial_omap_enable_ier_thri(up); return; } } spin_lock(&(up->uart_dma.tx_lock)); up->uart_dma.tx_dma_used = true; spin_unlock(&(up->uart_dma.tx_lock)); start = up->uart_dma.tx_buf_dma_phys + (xmit->tail & (UART_XMIT_SIZE - 1)); up->uart_dma.tx_buf_size = uart_circ_chars_pending(xmit); /* * It is a circular buffer. See if the buffer has wounded back. * If yes it will have to be transferred in two separate dma * transfers */ if (start + up->uart_dma.tx_buf_size >= up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) up->uart_dma.tx_buf_size = (up->uart_dma.tx_buf_dma_phys + UART_XMIT_SIZE) - start; omap_set_dma_dest_params(up->uart_dma.tx_dma_channel, 0, OMAP_DMA_AMODE_CONSTANT, up->uart_dma.uart_base, 0, 0); omap_set_dma_src_params(up->uart_dma.tx_dma_channel, 0, OMAP_DMA_AMODE_POST_INC, start, 0, 0); omap_set_dma_transfer_params(up->uart_dma.tx_dma_channel, OMAP_DMA_DATA_TYPE_S8, up->uart_dma.tx_buf_size, 1, OMAP_DMA_SYNC_ELEMENT, up->uart_dma.uart_dma_tx, 0); /* FIXME: Cache maintenance needed here? */ omap_start_dma(up->uart_dma.tx_dma_channel); }
static void serial_omap_console_write(struct console *co, const char *s, unsigned int count) { struct uart_omap_port *up = serial_omap_console_ports[co->index]; unsigned long flags; unsigned int ier; int console_lock = 0, locked = 1; if (console_trylock()) console_lock = 1; /* * If console_lock is not available and we are in suspending * state then we can avoid the console usage scenario * as this may introduce recursive prints. * Basically this scenario occurs during boot while * printing debug bootlogs. */ if (!console_lock && up->pdev->dev.power.runtime_status == RPM_SUSPENDING) return; local_irq_save(flags); if (up->port.sysrq) locked = 0; else if (oops_in_progress) locked = spin_trylock(&up->port.lock); else spin_lock(&up->port.lock); serial_omap_port_enable(up); /* * First save the IER then disable the interrupts */ ier = serial_in(up, UART_IER); serial_out(up, UART_IER, 0); uart_console_write(&up->port, s, count, serial_omap_console_putchar); /* * Finally, wait for transmitter to become empty * and restore the IER */ wait_for_xmitr(up); serial_out(up, UART_IER, ier); /* * The receive handling will happen properly because the * receive ready bit will still be set; it is not cleared * on read. However, modem control will not, we must * call it if we have saved something in the saved flags * while processing with interrupts off. */ if (up->msr_saved_flags) check_modem_status(up); if (console_lock) console_unlock(); serial_omap_port_disable(up); if (locked) spin_unlock(&up->port.lock); local_irq_restore(flags); }
static int serial_omap_probe(struct platform_device *pdev) { struct uart_omap_port *up = NULL; struct resource *mem, *irq, *dma_tx, *dma_rx; struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data; struct omap_device *od; int ret = -ENOSPC; mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!mem) { dev_err(&pdev->dev, "no mem resource?\n"); return -ENODEV; } irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); if (!irq) { dev_err(&pdev->dev, "no irq resource?\n"); return -ENODEV; } if (!request_mem_region(mem->start, (mem->end - mem->start) + 1, pdev->dev.driver->name)) { dev_err(&pdev->dev, "memory region already claimed\n"); return -EBUSY; } dma_rx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); if (!dma_rx) { ret = -EINVAL; goto err; } dma_tx = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); if (!dma_tx) { ret = -EINVAL; goto err; } up = kzalloc(sizeof(*up), GFP_KERNEL); if (up == NULL) { ret = -ENOMEM; goto do_release_region; } sprintf(up->name, "OMAP UART%d", pdev->id); up->pdev = pdev; up->port.dev = &pdev->dev; up->port.type = PORT_OMAP; up->port.iotype = UPIO_MEM; up->port.irq = irq->start; up->port.regshift = 2; up->port.fifosize = 64; up->port.ops = &serial_omap_pops; up->port.line = pdev->id; up->port.mapbase = mem->start; up->port.membase = ioremap(mem->start, mem->end - mem->start); if (!up->port.membase) { dev_err(&pdev->dev, "can't ioremap UART\n"); ret = -ENOMEM; goto err1; } up->port.flags = omap_up_info->flags; up->port.uartclk = omap_up_info->uartclk; up->uart_dma.uart_base = mem->start; up->errata = omap_up_info->errata; up->enable_wakeup = omap_up_info->enable_wakeup; up->wer = omap_up_info->wer; up->chk_wakeup = omap_up_info->chk_wakeup; up->wake_peer = omap_up_info->wake_peer; up->rts_mux_driver_control = omap_up_info->rts_mux_driver_control; up->rts_pullup_in_suspend = 0; up->wer_restore = 0; if (omap_up_info->use_dma) { up->uart_dma.uart_dma_tx = dma_tx->start; up->uart_dma.uart_dma_rx = dma_rx->start; up->use_dma = 1; up->uart_dma.rx_buf_size = omap_up_info->dma_rx_buf_size; up->uart_dma.rx_timeout = omap_up_info->dma_rx_timeout; up->uart_dma.rx_poll_rate = omap_up_info->dma_rx_poll_rate; spin_lock_init(&(up->uart_dma.tx_lock)); spin_lock_init(&(up->uart_dma.rx_lock)); up->uart_dma.tx_dma_channel = OMAP_UART_DMA_CH_FREE; up->uart_dma.rx_dma_channel = OMAP_UART_DMA_CH_FREE; } pm_runtime_use_autosuspend(&pdev->dev); pm_runtime_set_autosuspend_delay(&pdev->dev, omap_up_info->auto_sus_timeout); if (device_may_wakeup(&pdev->dev)) pm_runtime_enable(&pdev->dev); pm_runtime_irq_safe(&pdev->dev); if (omap_up_info->console_uart) { od = to_omap_device(up->pdev); omap_hwmod_idle(od->hwmods[0]); serial_omap_port_enable(up); serial_omap_port_disable(up); } ui[pdev->id] = up; serial_omap_add_console_port(up); ret = uart_add_one_port(&serial_omap_reg, &up->port); if (ret != 0) goto err1; dev_set_drvdata(&pdev->dev, up); platform_set_drvdata(pdev, up); return 0; err: dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n", pdev->id, __func__, ret); err1: kfree(up); do_release_region: release_mem_region(mem->start, (mem->end - mem->start) + 1); return ret; }