static void start_pmu(void * data) { int i; struct pmu_registers_a9 pmu_regs; bool is_start_paused; is_start_paused = *(bool *)data; pmu_regs.pmcr = 0x0; pmu_regs.ccnt = 0x0; pmu_regs.cntenset = 0x0; pmu_regs.cntenclr = 0x0; pmu_regs.intenset = 0x0; pmu_regs.intenclr = 0x0; pmu_regs.ovsr = 0x0; for (i=0; i<A9_PMN_NUM; i++) { pmu_regs.evtsel[i] = 0; pmu_regs.pmncnt[i] = 0; } /* disable PMU and clear CCNT & PMNx */ pmu_regs.pmcr = A9_Read_PMCR(); pmu_regs.pmcr &= ~0x1; pmu_regs.pmcr |= 0x6; A9_Write_PMCR(pmu_regs.pmcr); for (i=0; i<g_ebs_settings.eventNumber; i++) { switch (g_ebs_settings.event[i].registerId) { case COUNTER_A9_PMU_CCNT: set_ccnt_events(&g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_A9_PMU_PMN0: set_pmn_events(0, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_A9_PMU_PMN1: set_pmn_events(1, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_A9_PMU_PMN2: set_pmn_events(2, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_A9_PMU_PMN3: set_pmn_events(3, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_A9_PMU_PMN4: set_pmn_events(4, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_A9_PMU_PMN5: set_pmn_events(5, &g_ebs_settings.event[i], &pmu_regs); break; default: break; } } /* disable all counters */ A9_Write_CNTENCLR(0xffffffff); /* disable all interrupts */ A9_Write_INTENCLR(0xffffffff); /* clear overflow flags */ A9_Write_OVSR(0xffffffff); A9_Write_USEREN(0); /* write the counter values */ A9_WritePMUCounter(COUNTER_A9_PMU_CCNT, pmu_regs.ccnt); A9_WritePMUCounter(COUNTER_A9_PMU_PMN0, pmu_regs.pmncnt[0]); A9_WritePMUCounter(COUNTER_A9_PMU_PMN1, pmu_regs.pmncnt[1]); A9_WritePMUCounter(COUNTER_A9_PMU_PMN2, pmu_regs.pmncnt[2]); A9_WritePMUCounter(COUNTER_A9_PMU_PMN3, pmu_regs.pmncnt[3]); A9_WritePMUCounter(COUNTER_A9_PMU_PMN4, pmu_regs.pmncnt[4]); A9_WritePMUCounter(COUNTER_A9_PMU_PMN5, pmu_regs.pmncnt[5]); /* set events */ for (i=0; i<A9_PMN_NUM; i++) { A9_Write_PMNXSEL(i); A9_Write_PMNCNT(pmu_regs.pmncnt[i]); A9_Write_EVTSEL(pmu_regs.evtsel[i]); } pmu_regs.pmcr &= ~0x6; if (is_start_paused) { pmu_regs.pmcr &= ~0x1; } else { pmu_regs.pmcr |= 0x1; } /* enable the interrupts */ A9_Write_INTENSET(pmu_regs.intenset); /* enable the counters */ A9_Write_CNTENSET(pmu_regs.cntenset); /* Enable PMU */ A9_Write_PMCR(pmu_regs.pmcr); }
static int start_pmu(bool is_start_paused) { int i; int ret; struct pmu_registers_pj4 pmu_regs; pmu_regs.pmnc = 0x0; pmu_regs.ccnt = 0x0; pmu_regs.cntens = 0x0; pmu_regs.cntenc = 0x0; pmu_regs.intens = 0x0; pmu_regs.intenc = 0x0; pmu_regs.flag = 0x0; for (i=0; i<PJ4_PMN_NUM; i++) { pmu_regs.evtsel[i] = 0; pmu_regs.pmncnt[i] = 0; } ret = allocate_pmu(); if (ret != 0) { return ret; } ret = register_pmu_isr(px_css_isr); if (ret != 0) { return ret; } /* disable PMU and clear CCNT & PMNx */ pmu_regs.pmnc = PJ4_Read_PMNC(); pmu_regs.pmnc &= ~0x1; //pmu_regs.pmnc |= 0x6; PJ4_Write_PMNC(pmu_regs.pmnc); for (i=0; i<g_ebs_settings.eventNumber; i++) { switch (g_ebs_settings.event[i].registerId) { case COUNTER_PJ4_PMU_CCNT: set_ccnt_events(&g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PJ4_PMU_PMN0: set_pmn_events(0, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PJ4_PMU_PMN1: set_pmn_events(1, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PJ4_PMU_PMN2: set_pmn_events(2, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PJ4_PMU_PMN3: set_pmn_events(3, &g_ebs_settings.event[i], &pmu_regs); break; default: break; } } /* disable all counters */ PJ4_Write_CNTENC(0xffffffff); /* disable all interrupts */ PJ4_Write_INTENC(0xffffffff); /* clear overflow flags */ PJ4_Write_FLAG(0xffffffff); /* write the counter values */ PJ4_WritePMUCounter(COUNTER_PJ4_PMU_CCNT, pmu_regs.ccnt); PJ4_WritePMUCounter(COUNTER_PJ4_PMU_PMN0, pmu_regs.pmncnt[0]); PJ4_WritePMUCounter(COUNTER_PJ4_PMU_PMN1, pmu_regs.pmncnt[1]); PJ4_WritePMUCounter(COUNTER_PJ4_PMU_PMN2, pmu_regs.pmncnt[2]); PJ4_WritePMUCounter(COUNTER_PJ4_PMU_PMN3, pmu_regs.pmncnt[3]); /* set events */ for (i=0; i<PJ4_PMN_NUM; i++) { PJ4_Write_PMNXSEL(i); PJ4_Write_PMNCNT(pmu_regs.pmncnt[i]); PJ4_Write_EVTSEL(pmu_regs.evtsel[i]); } if (is_start_paused) { pmu_regs.pmnc &= ~0x1; } else { pmu_regs.pmnc |= 0x1; } /* enable the interrupts */ PJ4_Write_INTENS(pmu_regs.intens); /* enable the counters */ PJ4_Write_CNTENS(pmu_regs.cntens); /* Enable PMU */ PJ4_Write_PMNC(pmu_regs.pmnc); return 0; }
static int start_pmu(bool is_start_paused) { int i; int ret; struct pmu_registers_pxa2 pmu_regs; pmu_regs.pmnc = 0x0; pmu_regs.inten = 0x0; pmu_regs.flag = 0x0; pmu_regs.ccnt = 0x0; for (i=0; i<PXA2_PMN_NUM; i++) pmu_regs.pmn[i] = 0; pmu_regs.evtsel = 0x0; ret = allocate_pmu(); if (ret != 0) { return ret; } ret = register_pmu_isr(px_css_isr); if (ret != 0) { return ret; } pmu_regs.pmnc = 0x10; WritePMUReg(PXA2_PMU_PMNC, pmu_regs.pmnc); for (i=0; i<g_ebs_settings.eventNumber; i++) { switch (g_ebs_settings.event[i].registerId) { case COUNTER_PXA2_PMU_CCNT: set_ccnt_events(&g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PXA2_PMU_PMN0: set_pmn_events(0, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PXA2_PMU_PMN1: set_pmn_events(1, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PXA2_PMU_PMN2: set_pmn_events(2, &g_ebs_settings.event[i], &pmu_regs); break; case COUNTER_PXA2_PMU_PMN3: set_pmn_events(3, &g_ebs_settings.event[i], &pmu_regs); break; default: break; } } if (!is_start_paused) { pmu_regs.pmnc &= 0x0f; pmu_regs.pmnc |= 0x1; } WritePMUReg(PXA2_PMU_CCNT, pmu_regs.ccnt); WritePMUReg(PXA2_PMU_PMN0, pmu_regs.pmn[0]); WritePMUReg(PXA2_PMU_PMN1, pmu_regs.pmn[1]); WritePMUReg(PXA2_PMU_PMN2, pmu_regs.pmn[2]); WritePMUReg(PXA2_PMU_PMN3, pmu_regs.pmn[3]); WritePMUReg(PXA2_PMU_EVTSEL, pmu_regs.evtsel); WritePMUReg(PXA2_PMU_FLAG, pmu_regs.flag); WritePMUReg(PXA2_PMU_INTEN, pmu_regs.inten); WritePMUReg(PXA2_PMU_PMNC, pmu_regs.pmnc); return 0; }