static int __init setup_watchdog(char *str)
{
unsigned tmp;
int opt;
u8 ctr;
get_option(&str, &opt);
if (opt != 1)
return 0;
watchdog = opt;
if (watchdog) {
set_intr_stub(EXCEP_WDT, watchdog_handler);
ctr = WDCTR_WDCK_65536th;
WDCTR = WDCTR_WDRST | ctr;
WDCTR = ctr;
tmp = WDCTR;
tmp = __muldiv64u(1 << (16 + ctr * 2), 1000000, MN10300_WDCLK);
tmp = 1000000000 / tmp;
watchdog_hz = (tmp + 500) / 1000;
}
return 1;
}
/*
* initialise the profiling if enabled
* - using with gdbstub will give anomalous results
* - can't be used with gdbstub if running at IRQ priority 0
*/
static __init int profile_init(void)
{
u16 tmp;
if (!prof_buffer)
return 0;
/* use timer 11 to drive the profiling interrupts */
set_intr_stub(EXCEP_IRQ_LEVEL0, profile_handler);
/* set IRQ priority at which to run */
set_intr_level(TM11IRQ, GxICR_LEVEL_0);
/* set up timer 11
* - source: (IOCLK 33MHz)*2 = 66MHz
* - frequency: (33330000*2) / 8 / 20625 = 202Hz
*/
TM11BR = 20625 - 1;
TM11MD = TM8MD_SRC_IOCLK_8;
TM11MD |= TM8MD_INIT_COUNTER;
TM11MD &= ~TM8MD_INIT_COUNTER;
TM11MD |= TM8MD_COUNT_ENABLE;
TM11ICR |= GxICR_ENABLE;
tmp = TM11ICR;
printk(KERN_INFO "Profiling initiated on timer 11, priority 0, %uHz\n",
MN10300_IOCLK / 8 / (TM11BR + 1));
printk(KERN_INFO "Profile histogram stored %p-%p\n",
prof_buffer, (u8 *)(prof_buffer + prof_len) - 1);
return 0;
}
/*
* initialise the GDB stub I/O routines
*/
void __init gdbstub_io_init(void)
{
uint16_t scxctr;
int tmp;
switch (gdbstub_port->clock_src) {
case MNSCx_CLOCK_SRC_IOCLK:
gdbstub_port->ioclk = MN10300_IOCLK;
break;
#ifdef MN10300_IOBCLK
case MNSCx_CLOCK_SRC_IOBCLK:
gdbstub_port->ioclk = MN10300_IOBCLK;
break;
#endif
default:
BUG();
}
/* set up the serial port */
gdbstub_io_set_baud(115200);
/* we want to get serial receive interrupts */
set_intr_level(gdbstub_port->rx_irq, GxICR_LEVEL_0);
set_intr_level(gdbstub_port->tx_irq, GxICR_LEVEL_0);
set_intr_stub(EXCEP_IRQ_LEVEL0, gdbstub_io_rx_handler);
*gdbstub_port->rx_icr |= GxICR_ENABLE;
tmp = *gdbstub_port->rx_icr;
/* enable the device */
scxctr = SC01CTR_CLN_8BIT; /* 1N8 */
switch (gdbstub_port->div_timer) {
case MNSCx_DIV_TIMER_16BIT:
scxctr |= SC0CTR_CK_TM8UFLOW_8; /* == SC1CTR_CK_TM9UFLOW_8
== SC2CTR_CK_TM10UFLOW_8 */
break;
case MNSCx_DIV_TIMER_8BIT:
scxctr |= SC0CTR_CK_TM2UFLOW_8;
break;
}
scxctr |= SC01CTR_TXE | SC01CTR_RXE;
*gdbstub_port->_control = scxctr;
tmp = *gdbstub_port->_control;
/* permit level 0 IRQs only */
asm volatile(
" and %0,epsw \n"
" or %1,epsw \n"
:
: "i"(~EPSW_IM), "i"(EPSW_IE|EPSW_IM_1)
);
}
/*
* initialise the GDB stub I/O routines
*/
void __init gdbstub_io_init(void)
{
uint16_t scxctr;
int tmp;
switch (gdbstub_port->clock_src) {
case MNSCx_CLOCK_SRC_IOCLK:
gdbstub_port->ioclk = MN10300_IOCLK;
break;
#ifdef MN10300_IOBCLK
case MNSCx_CLOCK_SRC_IOBCLK:
gdbstub_port->ioclk = MN10300_IOBCLK;
break;
#endif
default:
BUG();
}
/* set up the serial port */
gdbstub_io_set_baud(115200);
/* we want to get serial receive interrupts */
set_intr_level(gdbstub_port->rx_irq,
NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL));
set_intr_level(gdbstub_port->tx_irq,
NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL));
set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL),
gdbstub_io_rx_handler);
*gdbstub_port->rx_icr |= GxICR_ENABLE;
tmp = *gdbstub_port->rx_icr;
/* enable the device */
scxctr = SC01CTR_CLN_8BIT; /* 1N8 */
switch (gdbstub_port->div_timer) {
case MNSCx_DIV_TIMER_16BIT:
scxctr |= SC0CTR_CK_TM8UFLOW_8; /* == SC1CTR_CK_TM9UFLOW_8
== SC2CTR_CK_TM10UFLOW_8 */
break;
case MNSCx_DIV_TIMER_8BIT:
scxctr |= SC0CTR_CK_TM2UFLOW_8;
break;
}
scxctr |= SC01CTR_TXE | SC01CTR_RXE;
*gdbstub_port->_control = scxctr;
tmp = *gdbstub_port->_control;
/* permit level 0 IRQs only */
arch_local_change_intr_mask_level(
NUM2EPSW_IM(CONFIG_DEBUGGER_IRQ_LEVEL + 1));
}
void __init gdbstub_io_init(void)
{
uint16_t scxctr;
int tmp;
switch (gdbstub_port->clock_src) {
case MNSCx_CLOCK_SRC_IOCLK:
gdbstub_port->ioclk = MN10300_IOCLK;
break;
#ifdef MN10300_IOBCLK
case MNSCx_CLOCK_SRC_IOBCLK:
gdbstub_port->ioclk = MN10300_IOBCLK;
break;
#endif
default:
BUG();
}
gdbstub_io_set_baud(115200);
set_intr_level(gdbstub_port->rx_irq,
NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL));
set_intr_level(gdbstub_port->tx_irq,
NUM2GxICR_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL));
set_intr_stub(NUM2EXCEP_IRQ_LEVEL(CONFIG_DEBUGGER_IRQ_LEVEL),
gdbstub_io_rx_handler);
*gdbstub_port->rx_icr |= GxICR_ENABLE;
tmp = *gdbstub_port->rx_icr;
scxctr = SC01CTR_CLN_8BIT;
switch (gdbstub_port->div_timer) {
case MNSCx_DIV_TIMER_16BIT:
scxctr |= SC0CTR_CK_TM8UFLOW_8;
break;
case MNSCx_DIV_TIMER_8BIT:
scxctr |= SC0CTR_CK_TM2UFLOW_8;
break;
}
scxctr |= SC01CTR_TXE | SC01CTR_RXE;
*gdbstub_port->_control = scxctr;
tmp = *gdbstub_port->_control;
arch_local_change_intr_mask_level(
NUM2EPSW_IM(CONFIG_DEBUGGER_IRQ_LEVEL + 1));
}