void bl(int i)
{
/*
I1 = NOT(J1 EOR S); I2 = NOT(J2 EOR S);
imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
if ConditionPassed() then
EncodingSpecificOperations();
next_instr_addr = PC;
LR = next_instr_addr<31:1> : '1';
SelectInstrSet(InstrSet_Thumb);
BranchWritePC(PC + imm32);
*/
int i1,i2,imm32,next_instr_addr;
*((int *)(&branchWithLink)) = i;
i1=!(branchWithLink.j1^branchWithLink.s);
i2=!(branchWithLink.j2^branchWithLink.s);
imm32=(branchWithLink.s<<24)|(i1<<23)|(i2<<22)|(branchWithLink.off2<<12)|(branchWithLink.off1<<1);
imm32 &= 0xFFFFFFFE;
//SignExtend
if(imm32 & 0x01000000)
imm32 |= 0xFE000000;
else
imm32 &= 0x01FFFFFF;
if(InITBlock() && !LastInITBlock())
printf("UNPREDICTABLE instruction.\n");
else{
EncodingSpecificOperations();
next_instr_addr=get_pc();
set_lr(next_instr_addr | 0x00000001);
//SelectInstrSet(InstrSet_Thumb); questionhi
BranchWritePC(get_pc()+imm32);
}
}
void Simulator::ResetState() {
// Reset the system registers.
nzcv_ = SimSystemRegister::DefaultValueFor(NZCV);
fpcr_ = SimSystemRegister::DefaultValueFor(FPCR);
// Reset registers to 0.
pc_ = NULL;
pc_modified_ = false;
for (unsigned i = 0; i < kNumberOfRegisters; i++) {
set_xreg(i, 0xbadbeef);
}
// Set FP registers to a value that is a NaN in both 32-bit and 64-bit FP.
uint64_t nan_bits = UINT64_C(0x7ff0dead7f8beef1);
VIXL_ASSERT(IsSignallingNaN(rawbits_to_double(nan_bits & kDRegMask)));
VIXL_ASSERT(IsSignallingNaN(rawbits_to_float(nan_bits & kSRegMask)));
for (unsigned i = 0; i < kNumberOfFPRegisters; i++) {
set_dreg_bits(i, nan_bits);
}
// Returning to address 0 exits the Simulator.
set_lr(kEndOfSimAddress);
set_resume_pc(nullptr);
}
