/*************************************
* ETH PINMUX SETTING
* More details can get from following:
* 1. am_eth_pinmux.h
* 2. AppNote-M3-CorePinMux.xlsx
* 3. m3_skt_v1.pdf
*************************************/
int aml_eth_set_pinmux(int bank_id,int clk_in_out_id,unsigned long ext_msk)
{
int ret=0;
switch(bank_id)
{
case ETH_BANK0_GPIOY1_Y9:
if(ext_msk>0)
set_mio_mux(ETH_BANK0_REG1,ext_msk);
else
set_mio_mux(ETH_BANK0_REG1,ETH_BANK0_REG1_VAL);
break;
default:
printf("UNknow pinmux setting of ethernet!error bankid=%d,must be 0-2\n",bank_id);
ret=-1;
}
switch(clk_in_out_id)
{
case ETH_CLK_IN_GPIOY0_REG6_18:
set_mio_mux(6,1<<18);
break;
case ETH_CLK_OUT_GPIOY0_REG6_17:
set_mio_mux(6,1<<17);
break;
default:
printf("UNknow clk_in_out_id setting of ethernet!error clk_in_out_id=%d,must be 0-9\n",clk_in_out_id);
ret=-1;
}
return ret;
}
static void set_tcon_pinmux(void)
{
/* TCON control pins pinmux */
/* GPIOA_5 -> TCON_CPH1:[11], GPIOA_0 -> TCON_STH1:[16], GPIOA_1 -> TCON_STV1:[15], GPIOA_2 -> TCON_OEH:[14], */
set_mio_mux(0, ((1<<11)|(1<<14)));
set_mio_mux(4, (1<<0)|(1<<2)|(1<<4) ); //For 6bits
}
static void __init device_pinmux_init(void )
{
clearall_pinmux();
/* other deivce power on */
/* GPIOA_200e_bit4..usb/eth/YUV power on */
//set_gpio_mode(PREG_EGPIO,1<<4,GPIO_OUTPUT_MODE);
//set_gpio_val(PREG_EGPIO,1<<4,1);
/* uart port A */
uart_set_pinmux(UART_PORT_A,UART_A_GPIO_B2_B3);
#ifndef CONFIG_I2C_SW_AML
/* uart port B */
uart_set_pinmux(UART_PORT_B,UART_B_GPIO_C13_C14);
//uart_set_pinmux(UART_PORT_B,UART_B_TCK_TDO);
#endif
/* pinmux of eth */
eth_pinmux_init();
/* IR decoder pinmux */
set_mio_mux(5, 1<<31);
#ifdef CONFIG_I2C_SW_AML /*for multak*/
/* SmartCard pinmux */
set_mio_mux(2, 0xF<<20);
#endif
set_audio_pinmux(AUDIO_IN_JTAG); // for MIC input
}
static void set_tcon_pinmux(void)
{
/* TCON control pins pinmux */
/* GPIOA_5 -> LCD_Clk, GPIOA_0 -> TCON_STH1, GPIOA_1 -> TCON_STV1, GPIOA_2 -> TCON_OEH, */
set_mio_mux(0, ((1<<11)|(1<<14)|(1<<15)|(1<<16)));
set_mio_mux(4,(3<<0)|(3<<2)|(3<<4)); //For 8bits
}
static void set_tcon_pinmux(void)
{
/* TCON control pins pinmux */
/* GPIOA_5 --> LCD_Clk, GPIOA_2 --> TCON_OEH, */
set_mio_mux(0, 1<<11);
set_mio_mux(0, 1<<14);
/* RGB data pins */
set_mio_mux(4,(1<<0)|(1<<2)|(1<<4));
}
static void set_tcon_pinmux(void)
{
/* TCON control pins pinmux */
/* GPIOA_5 -> LCD_Clk, GPIOA_0 -> TCON_STH1, GPIOA_1 -> TCON_STV1, GPIOA_2 -> TCON_OEH, */
set_mio_mux(0, ((1<<11)|(1<<14)|(1<<15)|(1<<16)));
set_mio_mux(4, (1<<0)|(1<<2)|(1<<4) ); //For 6bits
//PP1 -> UPDN:0, PP2 -> SHLR:1
#ifdef CONFIG_SN7325
configIO(1, 0);
setIO_level(1, 0, 1);
setIO_level(1, 1, 2);
#endif
}
static void set_tcon_pinmux(void)
{
debug("%s\n", __FUNCTION__);
/* TCON control pins pinmux */
clear_mio_mux(1, 0x0f<<11); // disable cph50(11),cph1(12),cph2(13),cph3(14)
#ifdef USE_CLKO
set_mio_mux(1, 1<<21); // enable clko
#else
set_mio_mux(1, 1<<14); // enable cph1
#endif
set_mio_mux(1, 1<<17); // enable oeh
set_mio_mux(0, 0x3f<<0); //For 8bits RGB
}
void board_nand_pinmux( unsigned int en_dis )
{
// printf("TODO SET A3 board pinmux");
if(en_dis)
set_mio_mux(4, (0x1<<11) | (0xff<<14));
else
clear_mio_mux(4, (0x1<<11) | (0xff<<14));
return;
}
static void __init device_pinmux_init(void )
{
clearall_pinmux();
/* uart port A */
uart_set_pinmux(UART_PORT_A,UART_A_GPIO_B2_B3);
/* uart port B */
uart_set_pinmux(UART_PORT_B,UART_B_TCK_TDO);
/* pinmux of eth */
eth_pinmux_init();
/* IR decoder pinmux */
set_mio_mux(5, 1<<31);
}
static void __init device_pinmux_init(void )
{
clearall_pinmux();
/* other deivce power on */
/* GPIOA_200e_bit4..usb/eth/YUV power on */
set_gpio_mode(PREG_EGPIO,1<<4,GPIO_OUTPUT_MODE);
set_gpio_val(PREG_EGPIO,1<<4,1);
uart_set_pinmux(UART_PORT_A,PINMUX_UART_A);
uart_set_pinmux(UART_PORT_B,PINMUX_UART_B);
/* pinmux of eth */
eth_pinmux_init();
/* IR decoder pinmux */
set_mio_mux(1, 1<<31);
//set_audio_pinmux(AUDIO_IN_JTAG); // for MIC input
}
/*ETH PINMUX SETTING
More details can get from am_eth_pinmux.h
*/
int eth_set_pinmux(int bank_id,int clk_in_out_id,unsigned long ext_msk)
{
int ret=0;
switch(bank_id)
{
case ETH_BANK0_GPIOC3_C12:
if(ext_msk>0)
set_mio_mux(ETH_BANK0_REG1,ext_msk);
else
set_mio_mux(ETH_BANK0_REG1,ETH_BANK0_REG1_VAL);
break;
case ETH_BANK1_GPIOD2_D11:
if(ext_msk>0)
set_mio_mux(ETH_BANK1_REG1,ext_msk);
else
set_mio_mux(ETH_BANK1_REG1,ETH_BANK1_REG1_VAL);
break;
case ETH_BANK2_GPIOD15_D23:
if(ext_msk>0)
set_mio_mux(ETH_BANK2_REG1,ext_msk);
else
set_mio_mux(ETH_BANK2_REG1,ETH_BANK2_REG1_VAL);
break;
default:
printk(KERN_ERR "UNknow pinmux setting of ethernet!error bankid=%d,must be 0-2\n",bank_id);
ret=-1;
}
switch(clk_in_out_id)
{
case ETH_CLK_IN_GPIOC2_REG4_26:
set_mio_mux(4,1<<26);
break;
case ETH_CLK_IN_GPIOC12_REG3_0:
set_mio_mux(3,1<<0);
break;
case ETH_CLK_IN_GPIOD7_REG4_19:
set_mio_mux(4,1<<19);
break;
case ETH_CLK_IN_GPIOD14_REG7_12:
set_mio_mux(7,1<<12);
break;
case ETH_CLK_IN_GPIOD24_REG5_0:
set_mio_mux(5,1<<0);
break;
case ETH_CLK_OUT_GPIOC2_REG4_27:
set_mio_mux(4,1<<27);
break;
case ETH_CLK_OUT_GPIOC12_REG3_1:
set_mio_mux(3,1<<1);
break;
case ETH_CLK_OUT_GPIOD7_REG4_20:
set_mio_mux(4,1<<20);
break;
case ETH_CLK_OUT_GPIOD14_REG7_13:
set_mio_mux(7,1<<13);
break;
case ETH_CLK_OUT_GPIOD24_REG5_1:
set_mio_mux(5,1<<1);
break;
default:
printk(KERN_ERR "UNknow clk_in_out_id setting of ethernet!error clk_in_out_id=%d,must be 0-9\n",clk_in_out_id);
ret=-1;
}
return ret;
}
/* --------------------------------------------------------------------------*/
static void __init set_audio_codec_pinmux(void)
{
/* for gpiox_17~20 I2S_AMCLK I2S_AOCLK I2S_LRCLK I2S_OUT */
clear_mio_mux(7, (1 << 18) | (1 << 19) | (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23));
set_mio_mux(8, (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24));
}
static void __init device_pinmux_init(void )
{
clearall_pinmux();
/*other deivce power on*/
/*GPIOA_200e_bit4..usb/eth/YUV power on*/
//set_gpio_mode(PREG_EGPIO,1<<4,GPIO_OUTPUT_MODE);
//set_gpio_val(PREG_EGPIO,1<<4,1);
//uart_set_pinmux(UART_PORT_A,PINMUX_UART_A);
//uart_set_pinmux(UART_PORT_B,PINMUX_UART_B);
/*pinmux of eth*/
eth_pinmux_init();
aml_i2c_init();
printk("SPDIF output.\n");
CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_0,(1<<19));
CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_3,(1<<25));
CLEAR_CBUS_REG_MASK(PERIPHS_PIN_MUX_7,(1<<17));
SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_3, (1<<24));
// set_audio_pinmux(AUDIO_OUT_TEST_N);
// set_audio_pinmux(AUDIO_IN_JTAG);
#ifdef CONFIG_AM_MXL101
//for mxl101
//set_mio_mux(3, 0x3F);
//clear_mio_mux(6, 0x1F<<19);
set_mio_mux(3, 0x3F<<6);
clear_mio_mux(0, 0xF);
clear_mio_mux(5, 0x1<<23);
clear_mio_mux(0, 1<<6);
//pwr pin;
clear_mio_mux(0, 1<<13);
clear_mio_mux(1, 1<<8);
//rst pin;
clear_mio_mux(0, 1<<28);
clear_mio_mux(1, 1<<20);
/* set_mio_mux(3, 1<<0);
set_mio_mux(3, 1<<1);
set_mio_mux(3, 1<<2);
set_mio_mux(3, 1<<3);
set_mio_mux(3, 1<<4);
clear_mio_mux(0, 1<<6);*/
#endif
#ifdef CONFIG_AM_AVL6211
//for avl6211
printk("CONFIG_AM_AVL6211 set pinmux\n");
set_mio_mux(3, 0x3F<<6);
// clear_mio_mux(0, 1<<4);
clear_mio_mux(0, 0x7);
#endif
#ifdef CONFIG_AM_ITE9173
//for ite9173
printk("CONFIG_AM_ITE9173 set pinmux\n");
set_mio_mux(3, 0x3F<<6);
// clear_mio_mux(0, 1<<4);
clear_mio_mux(0, 0x7);
#endif
#ifdef CONFIG_AM_RTL2830
//for rtl2830
printk("CONFIG_AM_RTL2830 set pinmux\n");
set_mio_mux(3, 0x3F<<6);
// clear_mio_mux(0, 1<<4);
clear_mio_mux(0, 0x7);
#endif
#ifdef CONFIG_AM_DS3000
//for rtl2830
printk("CONFIG_AM_DS3000 set pinmux\n");
set_mio_mux(3, 0x3F<<6);
// clear_mio_mux(0, 1<<4);
clear_mio_mux(0, 0x7);
#endif
#ifdef CONFIG_TH_SONY_T2
//for rtl2830
printk("CONFIG_AM_DS3000 set pinmux\n");
set_mio_mux(3, 0x3F<<6);
// clear_mio_mux(0, 1<<4);
clear_mio_mux(0, 0x7);
#endif
#ifdef CONFIG_AM_ITE9133
//for ite9133
printk("CONFIG_AM_ITE9133 set pinmux\n");
set_mio_mux(3, 0xFFF<<6);
// clear_mio_mux(0, 1<<4);
clear_mio_mux(0, 0x3F);
#endif
#ifdef CONFIG_AM_DIB7090P
printk("CONFIG_AM_DIB7090P set pinmux\n");
set_mio_mux(3, 0x3F<<6);
clear_mio_mux(0, 0xF);
clear_mio_mux(5, 0x1<<23);
/* clear_mio_mux(0, 1<<6);
//pwr pin;
clear_mio_mux(0, 1<<13);
clear_mio_mux(1, 1<<8);
//rst pin;
clear_mio_mux(0, 1<<28);
clear_mio_mux(1, 1<<20);*/
#endif
}
static int uVideoFmt_SetVideoType(control_t* cntl, cond_item_t* param)
{
int ret=0;
uvideofmt_t* uvideofmt = (uvideofmt_t*)(cntl->private_data);
int fmt = (int)(param[0]);
int outputmode = (int)(param[1]);
/* Add Method code here, Set ret to be -1 if fail */
int displayctl_fd, resolution_data;
video_appmode_t video_appmode =
{
DISPCTL_MODE_1080P,
0,
0,
0,
DISPCTL_MODE_1080P
};
page_t *page = af_find_page(SYSTEM_DEFAULT_PAGE);
if (this_curVideoFmt!=fmt || this_outputmode!= outputmode)
{
/* when NTSC/PAL CVBS output is enabled in first 3 video dacs,
* enable pedestal. Component 480i has pedestal disabled.
*/
#ifdef AML_NIKE
fmt = 6;
#endif
#ifndef EDGE_ADJUST
set_display_edge_adjust(0,0,0,0);
#endif
af_osd_layer_destroy(OSD_LAYER_HW_LAYER0);
switch(outputmode)
{
case 0://Analog
clear_mio_mux(5, (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<7));
//disable RGB data
//clear_mio_mux(4, (1<<20) | (1<<22) | (1<<24));//6bits
clear_mio_mux(4, (0x3f<<20));//8bits
#ifdef APOLLO_PMP_TVOUT
clear_mio_mux(4, 0x7c000000); //disable hdmi output ,
#endif
resolution_data = set_analog_output(fmt, &video_appmode);
break;
case 2://HDMI
clear_mio_mux(5, (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<7));
//disable RGB data
//clear_mio_mux(4, (1<<20) | (1<<22) | (1<<24));//6bits
clear_mio_mux(4, (0x3f<<20));//8bits
resolution_data = set_hdmi_output(fmt, &video_appmode);
set_mio_mux(4, 0x7c000000); //mux GPIOC_28 to hsync, mux GPIOC_29 to vsync, mux GPIOC_30 to DE, mux GPIOC_31 to pixel clock, mux GPIOC_32~GPIOC_55 to HDMI data lines,
Codec_PowerDown_Entile_Codec(0);
break;
#if (defined APOLLO_PMP_LCD) || (defined NIKE_PMP_LCD)
case 1://Panel
#ifdef EDGE_ADJUST
set_display_edge_adjust(0,0,0,0);
#endif
clear_mio_mux(4, 0x7c000000); //disable hdmi output ,
//enable Tcon
//set_mio_mux(5, (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<7) | (1<<8) | (1<<9));
set_mio_mux(5, (1<<0) | (1<<2) | (1<<3) | (1<<4) | (1<<7));
//enable RGB data
//set_mio_mux(4, (1<<20) | (1<<22) | (1<<24));//6bits
set_mio_mux(4, (0x3f<<20));//8bits
resolution_data = set_lcd_output(fmt, &video_appmode);
power_off_USBb();
break;
#endif
default:
AVOS_printf("Please select the valid output mode!\n");
break;
}
GF_SetHdmode(cntl, &video_appmode.hdmode);
af_set_current_resolution(resolution_data);
af_init_osd(page);
}
this_curVideoFmt_Set(fmt);
if(outputmode<=2&&outputmode>=0)
{
this_outputmode_Set(outputmode);
}
///////////////////////////////////////////
int video_fd;
video_fd=open("/dev/video",O_RDONLY);
//video_appmode_t video_appmode = {DISPCTL_MODE_480P, VIDEO_APPVMODE_480_480, VIDEO_APPHMODE_720, 0, DISPCTL_MODE_VGA};
video_appmode_t video_appmode2 = {DISPCTL_MODE_480P, VIDEO_APPVMODE_480_480, VIDEO_APPHMODE_720, 0, DISPCTL_MODE_VGA};
ioctl(video_fd, VIDEOIO_SETAPPMODE, &video_appmode2);
WRITE_MPEG_REG(VENC_VDAC_SETTING,0);
power_on_vdac();
///////////////////////////////////////////
AVTimeDly(100);
/* end */
return ret;
}
