static void configure_iva_dpll(dpll_param *dpll_param_p)
{
/* Unlock the IVA dpll */
set_modify(CM_CLKMODE_DPLL_IVA, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_IVA);
/* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */
set_modify(CM_BYPCLK_DPLL_IVA, 0x00000003, 0x1);
/* Disable DPLL autoidle */
set_modify(CM_AUTOIDLE_DPLL_IVA, 0x00000007, 0x0);
/* Set M,N,M4,M5 */
set_modify(CM_CLKSEL_DPLL_IVA, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_IVA, 0x0000007f, dpll_param_p->n);
set_modify(CM_DIV_M4_DPLL_IVA, 0x0000001f, dpll_param_p->m4);
set_modify(CM_DIV_M4_DPLL_IVA, 0x00000100, 0x1 << 8);
set_modify(CM_DIV_M5_DPLL_IVA, 0x0000001f, dpll_param_p->m5);
set_modify(CM_DIV_M5_DPLL_IVA, 0x00000100, 0x1 << 8);
/* Lock the iva dpll */
set_modify(CM_CLKMODE_DPLL_IVA, 0x00000007, PLL_LOCK);
check_loop(BIT0, 1, CM_IDLEST_DPLL_IVA);
}
static void configure_mpu_dpll(dpll_param *dpll_param_p,
struct proc_specific_functions *proc_ops)
{
int omap_rev;
u32 emif_div_4, abe_div_8, dcc_en;
/* Unlock the MPU dpll */
set_modify(CM_CLKMODE_DPLL_MPU, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_MPU);
omap_rev = proc_ops->proc_get_proc_id();
if (omap_rev >= OMAP_4470_ES1_DOT_0) {
/*
* Same M, N as for 800 MHz from M2 output will
* give 1600 MHz from M3 output
*/
dpll_param_p = &mpu_dpll_param_800mhz;
} else if (omap_rev >= OMAP_4460_ES1_DOT_0) {
/*
* Same M, N as for 700 MHz from M2 output will
* give 1400 MHz from M3 output
*/
dpll_param_p = &mpu_dpll_param_700mhz;
emif_div_4 = 1;
abe_div_8 = 1;
set_modify(CM_MPU_MPU_CLKCTRL, 0x01000000, emif_div_4 << 24);
set_modify(CM_MPU_MPU_CLKCTRL, 0x02000000, abe_div_8 << 25);
dcc_en = 0;
/* Enable / disable DCC on 4460 */
set_modify(CM_CLKSEL_DPLL_MPU, 0x00400000, dcc_en << 22);
}
/* Disable DPLL autoidle */
set_modify(CM_AUTOIDLE_DPLL_MPU, 0x00000007, 0x0);
/* Set M,N,M2 values */
set_modify(CM_CLKSEL_DPLL_MPU, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_MPU, 0x0000003f, dpll_param_p->n);
set_modify(CM_DIV_M2_DPLL_MPU, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M2_DPLL_MPU, 0x00000100, 0x1 << 8);
/* Lock the mpu dpll */
set_modify(CM_CLKMODE_DPLL_MPU, 0x00000007, (PLL_LOCK | 10));
check_loop(BIT0, 1, CM_IDLEST_DPLL_MPU);
}
void configure_smartio(struct smartio *smartio_config)
{
struct smartio *smartio;
if (smartio_config != NULL) {
for (smartio = &smartio_config[0]; smartio->base > 0;
smartio++)
set_modify(smartio->base, smartio->mask,
smartio->value);
} else {
for (smartio = &smartio_default[0]; smartio->base > 0;
smartio++)
set_modify(smartio->base, smartio->mask,
smartio->value);
}
}
/* must be called from sram or flash */
void gpmc_init(void)
{
u32 cs_base = GPMC_CONFIG_CS0;
u8 i;
/* Disable all Chip Selects as there is
* no device on gpmc right now
*/
for (i = 0; i < 8; i++)
set_modify(cs_base + GPMC_CONFIG7 + 0x30*i, 0x00000040, 0 << 6);
return;
}
static int omap5evm_check_fastboot(void)
{
u32 temp;
/* set the clock for the keypad */
set_modify(CM_WKUPAON_KBD_CLKCTRL, 0x00000003, 0x02);
/* any key pressed ? */
temp = readl(KBD_STATEMACHINE);
if (temp == 0)
return 0;
ldelay(200000);
temp = readl(KBD_FULLCODE31_0);
if ((temp & USER_FASTBOOT_RQ) == USER_FASTBOOT_RQ) {
printf("Keypress detected: going to fastboot mode\n");
return 1;
}
return 0;
}
/**
* scale_vcore_omap4460() - Scale for OMAP4460
* @rev: OMAP chip revision
*
* PMIC assumed to be used is TWL6030 + TPS62361
*/
static void scale_vcore_omap4460(unsigned int rev)
{
u32 volt;
/* vdd_core - TWL6030 VCORE 1 - OPP100 - 1.127V */
omap_vc_bypass_send_value(TWL6030_SRI2C_SLAVE_ADDR,
TWL6030_SRI2C_REG_ADDR_VCORE1, 0x22);
/* WKUP clocks */
set_modify(CM_WKUP_GPIO1_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL);
/* vdd_mpu - TPS62361 - OPP100 - 1.210V (roundup from 1.2V) */
volt = 1210;
volt -= TPS62361_BASE_VOLT_MV;
volt /= 10;
do_scale_tps62361(TPS62361_REG_ADDR_SET1, volt);
/* vdd_iva - TWL6030 VCORE 2 - OPP50 - 0.950V */
omap_vc_bypass_send_value(TWL6030_SRI2C_SLAVE_ADDR,
TWL6030_SRI2C_REG_ADDR_VCORE2, 0x14);
}
static void configure_mpu_dpll(dpll_param *dpll_param_p)
{
/* Unlock the MPU dpll */
set_modify(CM_CLKMODE_DPLL_MPU, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_MPU);
/* Disable DPLL autoidle */
set_modify(CM_AUTOIDLE_DPLL_MPU, 0x00000007, 0x0);
/* Set M,N,M2 values */
set_modify(CM_CLKSEL_DPLL_MPU, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_MPU, 0x0000003f, dpll_param_p->n);
set_modify(CM_DIV_M2_DPLL_MPU, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M2_DPLL_MPU, 0x00000100, 0x1 << 8);
/* Lock the mpu dpll */
set_modify(CM_CLKMODE_DPLL_MPU, 0x00000007, (PLL_LOCK | 10));
check_loop(BIT0, 1, CM_IDLEST_DPLL_MPU);
}
static void enable_all_clocks(void)
{
/* L4PER clocks */
set_modify(CM_L4PER_CLKSTCTRL, 0x00000000, 0x2);
set_modify(CM_L4PER_DMTIMER10_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_DMTIMER10_CLKCTRL);
set_modify(CM_L4PER_DMTIMER11_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_DMTIMER11_CLKCTRL);
set_modify(CM_L4PER_DMTIMER2_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_DMTIMER2_CLKCTRL);
set_modify(CM_L4PER_DMTIMER3_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_DMTIMER3_CLKCTRL);
set_modify(CM_L4PER_DMTIMER4_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_DMTIMER4_CLKCTRL);
set_modify(CM_L4PER_DMTIMER9_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_DMTIMER9_CLKCTRL);
/* GPIO clocks */
set_modify(CM_L4PER_GPIO2_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L4PER_GPIO2_CLKCTRL);
set_modify(CM_L4PER_GPIO3_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L4PER_GPIO3_CLKCTRL);
set_modify(CM_L4PER_GPIO4_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L4PER_GPIO4_CLKCTRL);
set_modify(CM_L4PER_GPIO4_CLKCTRL, 0x00000100, 0x1 << 8);
set_modify(CM_L4PER_GPIO5_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L4PER_GPIO5_CLKCTRL);
set_modify(CM_L4PER_GPIO6_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L4PER_GPIO6_CLKCTRL);
set_modify(CM_L4PER_HDQ1W_CLKCTRL, 0x00000000, 0x2);
/* I2C clocks */
set_modify(CM_L4PER_I2C1_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_I2C1_CLKCTRL);
set_modify(CM_L4PER_I2C2_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_I2C2_CLKCTRL);
set_modify(CM_L4PER_I2C3_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_I2C3_CLKCTRL);
set_modify(CM_L4PER_I2C4_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_I2C4_CLKCTRL);
set_modify(CM_L4PER_MCBSP4_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_MCBSP4_CLKCTRL);
/* MCSPI clocks */
set_modify(CM_L4PER_MCSPI1_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_MCSPI1_CLKCTRL);
set_modify(CM_L4PER_MCSPI2_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_MCSPI2_CLKCTRL);
set_modify(CM_L4PER_MCSPI3_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_MCSPI3_CLKCTRL);
set_modify(CM_L4PER_MCSPI4_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL);
/* MMC clocks */
set_modify(CM_L3INIT_HSMMC1_CLKCTRL, 0x00000003, 0x2);
set_modify(CM_L3INIT_HSMMC1_CLKCTRL, 0x01000000, 0x1 << 24);
set_modify(CM_L3INIT_HSMMC2_CLKCTRL, 0x00000003, 0x2);
set_modify(CM_L3INIT_HSMMC2_CLKCTRL, 0x01000000, 0x1 << 24);
set_modify(CM_L4PER_MMCSD3_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL);
set_modify(CM_L4PER_MMCSD4_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD4_CLKCTRL);
set_modify(CM_L4PER_MMCSD5_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_MMCSD5_CLKCTRL);
/* UART clocks */
set_modify(CM_L4PER_UART1_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_UART1_CLKCTRL);
set_modify(CM_L4PER_UART2_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_UART2_CLKCTRL);
set_modify(CM_L4PER_UART3_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_UART3_CLKCTRL);
set_modify(CM_L4PER_UART4_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_L4PER_UART4_CLKCTRL);
/* WKUP clocks */
set_modify(CM_WKUP_GPIO1_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL);
set_modify(CM_WKUP_TIMER1_CLKCTRL, 0x00000000, 0x01000002);
check_loop(BIT17|BIT16, 0, CM_WKUP_TIMER1_CLKCTRL);
set_modify(CM_WKUP_KEYBOARD_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_WKUP_KEYBOARD_CLKCTRL);
set_modify(CM_SDMA_CLKSTCTRL, 0x00000000, 0x0);
set_modify(CM_MEMIF_CLKSTCTRL, 0x00000000, 0x3);
set_modify(CM_MEMIF_EMIF_1_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_MEMIF_EMIF_1_CLKCTRL);
set_modify(CM_MEMIF_EMIF_2_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_MEMIF_EMIF_2_CLKCTRL);
set_modify(CM_D2D_CLKSTCTRL, 0x00000000, 0x3);
set_modify(CM_L3_2_GPMC_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L3_2_GPMC_CLKCTRL);
set_modify(CM_L3INSTR_L3_3_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L3INSTR_L3_3_CLKCTRL);
set_modify(CM_L3INSTR_L3_INSTR_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L3INSTR_L3_INSTR_CLKCTRL);
set_modify(CM_L3INSTR_OCP_WP1_CLKCTRL, 0x00000000, 0x1);
check_loop(BIT17|BIT16, 0, CM_L3INSTR_OCP_WP1_CLKCTRL);
/* WDT clocks */
set_modify(CM_WKUP_WDT2_CLKCTRL, 0x00000000, 0x2);
check_loop(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL);
/* Select DPLL PER CLOCK as source for SGX FCLK */
set_modify(CM_SGX_SGX_CLKCTRL, 0x01000000, 0x1 << 24);
/* Enable clocks for USB fast boot to work */
set_modify(CM_L3INIT_USBPHY_CLKCTRL, 0x00000000, 0x301);
set_modify(CM_L3INIT_HSUSBOTG_CLKCTRL, 0x00000000, 0x1);
return;
}
void lock_core_dpll(void)
{
/* Lock the core dpll */
set_modify(CM_CLKMODE_DPLL_CORE, 0x00000007, PLL_LOCK);
check_loop(BIT0, 1, CM_IDLEST_DPLL_CORE);
}
void configure_core_dpll_no_lock(void)
{
dpll_param *dpll_param_p = &core_dpll_param_ddr400mhz;
/* Get the sysclk speed from cm_sys_clksel
* Set it to 38.4 MHz, in case ROM code is bypassed
*/
writel(0x7,CM_SYS_CLKSEL);
/* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
set_modify(CM_CLKSEL_CORE, 0x00000000, 0x110);
/* Unlock the CORE dpll */
set_modify(CM_CLKMODE_DPLL_CORE, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_CORE);
/* Disable autoidle */
set_modify(CM_AUTOIDLE_DPLL_CORE, 0x00000007, 0x0);
set_modify(CM_CLKSEL_DPLL_CORE, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_CORE, 0x0000003f, dpll_param_p->n);
set_modify(CM_DIV_M2_DPLL_CORE, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M3_DPLL_CORE, 0x0000001f, dpll_param_p->m3);
set_modify(CM_DIV_M4_DPLL_CORE, 0x0000001f, dpll_param_p->m4);
set_modify(CM_DIV_M5_DPLL_CORE, 0x0000001f, dpll_param_p->m5);
set_modify(CM_DIV_M6_DPLL_CORE, 0x0000001f, dpll_param_p->m6);
set_modify(CM_DIV_M7_DPLL_CORE, 0x0000001f, dpll_param_p->m7);
}
static void configure_usb_dpll(dpll_param *dpll_param_p)
{
/* Select the 60Mhz clock 480/8 = 60*/
set_modify(CM_CLKSEL_USB_60MHz, 0x00000000, 0x1);
/* Unlock the USB dpll */
set_modify(CM_CLKMODE_DPLL_USB, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_USB);
/* Disable autoidle */
set_modify(CM_AUTOIDLE_DPLL_USB, 0x00000007, 0x0);
set_modify(CM_CLKSEL_DPLL_USB, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_USB, 0x0000003f, dpll_param_p->n);
/* Force DPLL CLKOUT to stay active */
set_modify(CM_DIV_M2_DPLL_USB, 0x00000000, 0x100);
set_modify(CM_DIV_M2_DPLL_USB, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M2_DPLL_USB, 0x00000100, 0x1 << 8);
set_modify(CM_CLKDCOLDO_DPLL_USB, 0x00000100, 0x1 << 8);
/* Lock the usb dpll */
set_modify(CM_CLKMODE_DPLL_USB, 0x00000007, PLL_LOCK);
check_loop(BIT0, 1, CM_IDLEST_DPLL_USB);
/* force enable the CLKDCOLDO clock */
set_modify(CM_CLKDCOLDO_DPLL_USB, 0x00000000, 0x100);
}
static void configure_abe_dpll(dpll_param *dpll_param_p)
{
/* Select sys_clk as ref clk for ABE dpll */
writel(0, CM_ABE_PLL_REF_CLKSEL);
/* Unlock the ABE dpll */
set_modify(CM_CLKMODE_DPLL_ABE, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_ABE);
/* Disable autoidle */
set_modify(CM_AUTOIDLE_DPLL_ABE, 0x00000007, 0x0);
set_modify(CM_CLKSEL_DPLL_ABE, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_ABE, 0x0000002f, dpll_param_p->n);
/* Force DPLL CLKOUTHIF to stay enabled */
set_modify(CM_DIV_M2_DPLL_ABE, 0x00000000, 0x500);
set_modify(CM_DIV_M2_DPLL_ABE, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M2_DPLL_ABE, 0x00000100, 0x1 << 8);
/* Force DPLL CLKOUTHIF to stay enabled */
set_modify(CM_DIV_M3_DPLL_ABE, 0x00000000, 0x100);
set_modify(CM_DIV_M3_DPLL_ABE, 0x0000001f, dpll_param_p->m3);
set_modify(CM_DIV_M3_DPLL_ABE, 0x00000100, 0x1 << 8);
/* Lock the abe dpll */
set_modify(CM_CLKMODE_DPLL_ABE, 0x00000007, PLL_LOCK);
check_loop(BIT0, 1, CM_IDLEST_DPLL_ABE);
}
static void configure_per_dpll(const dpll_param *dpll_param_p)
{
/* Unlock the PER dpll */
set_modify(CM_CLKMODE_DPLL_PER, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_PER);
/* Disable autoidle */
set_modify(CM_AUTOIDLE_DPLL_PER, 0x00000007, 0x0);
set_modify(CM_CLKSEL_DPLL_PER, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_PER, 0x0000003f, dpll_param_p->n);
set_modify(CM_DIV_M2_DPLL_PER, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M2_DPLL_PER, 0x00000100, 0x1 << 8);
set_modify(CM_DIV_M3_DPLL_PER, 0x0000001f, dpll_param_p->m3);
set_modify(CM_DIV_M3_DPLL_PER, 0x00000100, 0x1 << 8);
set_modify(CM_DIV_M4_DPLL_PER, 0x0000001f, dpll_param_p->m4);
set_modify(CM_DIV_M4_DPLL_PER, 0x00000100, 0x1 << 8);
set_modify(CM_DIV_M5_DPLL_PER, 0x0000001f, dpll_param_p->m5);
set_modify(CM_DIV_M5_DPLL_PER, 0x00000100, 0x1 << 8);
set_modify(CM_DIV_M6_DPLL_PER, 0x0000001f, dpll_param_p->m6);
set_modify(CM_DIV_M6_DPLL_PER, 0x00000100, 0x1 << 8);
set_modify(CM_DIV_M7_DPLL_PER, 0x0000001f, dpll_param_p->m7);
set_modify(CM_DIV_M7_DPLL_PER, 0x00000100, 0x1 << 8);
/* Lock the per dpll */
set_modify(CM_CLKMODE_DPLL_PER, 0x00000007, PLL_LOCK);
check_loop(BIT0, 1, CM_IDLEST_DPLL_PER);
}
void configure_core_dpll_no_lock(struct proc_specific_functions *proc_ops)
{
int omap_rev;
dpll_param *dpll_param_p;
omap_rev = proc_ops->proc_get_proc_id();
if (omap_rev >= OMAP_4470_ES1_DOT_0)
dpll_param_p = &core_dpll_param_ddr466mhz;
else
dpll_param_p = &core_dpll_param_ddr400mhz;
/* Get the sysclk speed from cm_sys_clksel
* Set it to 38.4 MHz, in case ROM code is bypassed
*/
writel(0x7,CM_SYS_CLKSEL);
/* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */
set_modify(CM_CLKSEL_CORE, 0x00000000, 0x110);
/* Unlock the CORE dpll */
set_modify(CM_CLKMODE_DPLL_CORE, 0x00000007, PLL_MN_POWER_BYPASS);
check_loop(BIT0, 0, CM_IDLEST_DPLL_CORE);
/* Disable autoidle */
set_modify(CM_AUTOIDLE_DPLL_CORE, 0x00000007, 0x0);
set_modify(CM_CLKSEL_DPLL_CORE, 0x0007ff00, dpll_param_p->m << 8);
set_modify(CM_CLKSEL_DPLL_CORE, 0x0000003f, dpll_param_p->n);
set_modify(CM_DIV_M2_DPLL_CORE, 0x0000001f, dpll_param_p->m2);
set_modify(CM_DIV_M3_DPLL_CORE, 0x0000001f, dpll_param_p->m3);
set_modify(CM_DIV_M4_DPLL_CORE, 0x0000001f, dpll_param_p->m4);
set_modify(CM_DIV_M5_DPLL_CORE, 0x0000001f, dpll_param_p->m5);
set_modify(CM_DIV_M6_DPLL_CORE, 0x0000001f, dpll_param_p->m6);
set_modify(CM_DIV_M7_DPLL_CORE, 0x0000001f, dpll_param_p->m7);
}
