static void fixup_store(struct disasm_state *state, struct pt_regs *regs,
struct callee_regs *cregs)
{
/* register write back */
if ((state->aa == 1) || (state->aa == 2)) {
set_reg(state->wb_reg, state->src2 + state->src3, regs, cregs);
if (state->aa == 3)
state->src3 = 0;
} else if (state->aa == 3) {
if (state->zz == 2) {
set_reg(state->wb_reg, state->src2 + (state->src3 << 1),
regs, cregs);
} else if (!state->zz) {
set_reg(state->wb_reg, state->src2 + (state->src3 << 2),
regs, cregs);
} else {
goto fault;
}
}
/* write fix-up */
if (!state->zz)
put32_unaligned_check(state->src1, state->src2 + state->src3);
else
put16_unaligned_check(state->src1, state->src2 + state->src3);
return;
fault: state->fault = 1;
}
void single_frame_update(struct hisi_fb_data_type *hisifd)
{
char __iomem *dss_base = NULL;
BUG_ON(hisifd == NULL);
dss_base = hisifd->dss_base;
if (hisifd->index == PRIMARY_PANEL_IDX) {
if (is_mipi_cmd_panel(hisifd)) {
set_reg(dss_base + PDP_LDI_FRM_MSK, 1, 1, 24);
}
set_reg(dss_base + PDP_LDI_CTRL, 1, 1, 0);
} else if (hisifd->index == EXTERNAL_PANEL_IDX) {
if (is_mipi_cmd_panel(hisifd)) {
set_reg(dss_base + SDP_LDI_FRM_MSK, 1, 1, 24);
}
set_reg(dss_base + SDP_LDI_CTRL, 1, 1, 0);
} else {
;
}
if (hisifd->vsync_ctrl.vsync_report_fnc) {
atomic_inc(&(hisifd->vsync_ctrl.buffer_updated));
}
}
static int hisi_offlinecompser_panel_off(struct platform_device *pdev)
{
int ret = 0;
struct hisi_fb_data_type *hisifd = NULL;
int i = 0;
BUG_ON(pdev == NULL);
hisifd = platform_get_drvdata(pdev);
BUG_ON(hisifd == NULL);
HISI_FB_DEBUG("index=%d, enter!\n", hisifd->index);
for (i = 0; i < HISI_DSS_OFFLINE_MAX_NUM; i++) {
char __iomem *ctl_base = hisifd->dss_base + DSS_GLB_WBE1_CH0_CTL +
i * (DSS_GLB_WBE1_CH1_CTL - DSS_GLB_WBE1_CH0_CTL);
cmdlist_config_stop(hisifd, i);
hisifd->offline_wb_status[i] = e_status_idle;
set_reg(ctl_base, 0x1, 1, 8);
set_reg(ctl_base, 0x0, 1, 8);
}
HISI_FB_DEBUG("index=%d, exit!\n", hisifd->index);
return ret;
}
int emu_step() {
instruction in;
int i;
char *state;
int result;
in.instr = read_insrtuction(memory.R[7]);
memset(disas, '0', LEN);
memset(reg, '0', LEN);
for (i = 0; i < COUNT; i++) {
if (check_instr(i, in)) {
sprintf(disas, "%06o %s", in.instr, table[i].assembler(in));
result = handle_callback(i, in);
switch(result) {
case EX:
state = "Execution";
break;
case HLT:
state = "Completed";
break;
default:
state = "Unknown error";
}
set_reg(state);
return in.instr;
}
}
sprintf(disas, "%s", "UNKNOWN COMMAND");
set_reg("ERROR UNKNOWN OPCODE");
return UNKNOWN_COMMAND;
}
static void fixup_load(struct disasm_state *state, struct pt_regs *regs,
struct callee_regs *cregs)
{
int val;
/* register write back */
if ((state->aa == 1) || (state->aa == 2)) {
set_reg(state->wb_reg, state->src1 + state->src2, regs, cregs);
if (state->aa == 2)
state->src2 = 0;
}
if (state->zz == 0) {
get32_unaligned_check(val, state->src1 + state->src2);
} else {
get16_unaligned_check(val, state->src1 + state->src2);
if (state->x)
val = (val << 16) >> 16;
}
if (state->pref == 0)
set_reg(state->dest, val, regs, cregs);
return;
fault: state->fault = 1;
}
static int mipi_dsi_frc_handle(struct platform_device *pdev, int fps)
{
int ret = 0;
#if 0
struct hisi_fb_data_type *hisifd = NULL;
struct hisi_panel_info *pinfo = NULL;
uint32_t hline_time = 0;
uint32_t pixel_clk = 0;
uint32_t vertical_timing = 0;
uint32_t horizontal_timing = 0;
uint32_t h_front_porch = 0;
BUG_ON(pdev == NULL);
hisifd = platform_get_drvdata(pdev);
BUG_ON(hisifd == NULL);
if (hisifd->index != PRIMARY_PANEL_IDX) {
HISI_FB_ERR("fb%d, not support!", hisifd->index);
return 0;
}
HISI_FB_DEBUG("fb%d, +.\n", hisifd->index);
pinfo = &(hisifd->panel_info);
/* calculate new HFP based on target_fps */
vertical_timing = pinfo->yres + pinfo->ldi.v_back_porch
+ pinfo->ldi.v_front_porch + pinfo->ldi.v_pulse_width;
horizontal_timing = pinfo->pxl_clk_rate / (vertical_timing * fps);
/* new HFP*/
/*
pinfo->ldi.h_front_porch = horizontal_timing - pinfo->xres
-pinfo->ldi.h_back_porch - pinfo->ldi.h_pulse_width;
*/
h_front_porch = horizontal_timing - pinfo->xres
-pinfo->ldi.h_back_porch - pinfo->ldi.h_pulse_width;
pixel_clk = pinfo->pxl_clk_rate / 1000000;
/* update hline_time */
hline_time = (pinfo->ldi.h_pulse_width + pinfo->ldi.h_back_porch +
pinfo->xres + h_front_porch) *
(pinfo->mipi.dsi_bit_clk / 4) / pixel_clk;
/* reset dsi core */
set_reg(hisifd->mipi_dsi0_base + MIPIDSI_PWR_UP_OFFSET, 0x0, 1, 0);
set_reg(hisifd->mipi_dsi0_base + MIPIDSI_VID_HLINE_TIME_OFFSET, hline_time, 15, 0);
outp32(hisifd->dss_base + PDP_LDI_DPI0_HRZ_CTRL0,
h_front_porch | (pinfo->ldi.h_back_porch << 16));
/* power on dsi core */
set_reg(hisifd->mipi_dsi0_base + MIPIDSI_PWR_UP_OFFSET, 0x1, 1, 0);
HISI_FB_DEBUG("fb%d, -.\n", hisifd->index);
#endif
return ret;
}
virtual void set_bit(sys_bus_addr addr, int pos, bool enable) {
uint32_t reg = get_reg(addr);
if (enable) {
set_reg(addr, (reg | (1 << pos)));
} else {
set_reg(addr, (reg & ~(1 << pos)));
}
}
void disable_clk_adp(struct hisi_fb_data_type *hisifd)
{
disable_clk_axi(hisifd);
disable_clk_rot1(hisifd);
disable_clk_dpe2(hisifd);
set_reg(hisifd->dss_base + DSS_GLB_DPE2_CLK_SW, 0x0, 1, 0);
set_reg(hisifd->dss_base + DSS_GLB_ROT1_CLK_SW, 0x0, 1, 0);
}
static int hh2serial_disable(struct connman_device *device)
{
DBG("");
set_reg("/sys/class/gpio/expo_rt", "85");
set_reg("/sys/class/gpio/gpio85/direction", "out");
set_reg("/sys/class/gpio/gpio85/value", "0");
return 0;
}
int init_new_thread(SysStruct *ss, int (*f)())
{
int pid;
if(ss == NULL)
return -1;
pid = get_next_avail_pid(ss);
if(pid < 0 || pid >= NUM_PROCS)
return -1;
set_reg(ss, pid, SP_REG, (int)(ss->proc[pid].stack + STACK_SIZE));
set_reg(ss, pid, LR_REG, (int)end_process);
set_reg(ss, pid, PC_REG, (int)f);
set_spsr(ss, pid, 0x10);
return pid;
}
static int ldi_init(struct k3_fb_data_type *k3fd)
{
u32 edc_base = 0;
struct k3_panel_info *pinfo = NULL;
BUG_ON(k3fd == NULL);
pinfo = &(k3fd->panel_info);
edc_base = k3fd->edc_base;
set_LDI_HRZ_CTRL0_hfp(edc_base, pinfo->ldi.h_front_porch);
set_LDI_HRZ_CTRL0_hbp(edc_base, pinfo->ldi.h_back_porch);
set_LDI_HRZ_CTRL1_hsw(edc_base, pinfo->ldi.h_pulse_width);
set_LDI_VRT_CTRL0_vfp(edc_base, pinfo->ldi.v_front_porch);
set_LDI_VRT_CTRL0_vbp(edc_base, pinfo->ldi.v_back_porch);
if (pinfo->ldi.v_pulse_width > 15)
pinfo->ldi.v_pulse_width = 15;
set_LDI_VRT_CTRL1_vsw(edc_base, pinfo->ldi.v_pulse_width);
set_LDI_PLR_CTRL_hsync(edc_base, pinfo->ldi.hsync_plr);
set_LDI_PLR_CTRL_vsync(edc_base, pinfo->ldi.vsync_plr);
set_LDI_PLR_CTRL_pixel_clk(edc_base, pinfo->ldi.pixelclk_plr);
set_LDI_PLR_CTRL_data_en(edc_base, pinfo->ldi.data_en_plr);
set_LDI_DSP_SIZE_hsize(edc_base, pinfo->xres);
set_LDI_DSP_SIZE_vsize(edc_base, pinfo->yres);
set_LDI_WORK_MODE_work_mode(edc_base, LDI_WORK);
set_LDI_WORK_MODE_colorbar_en(edc_base, K3_DISABLE);
set_LDI_CTRL_bgr(edc_base, pinfo->bgr_fmt);
set_LDI_CTRL_bpp(edc_base, pinfo->bpp);
set_LDI_CTRL_disp_mode(edc_base, pinfo->ldi.disp_mode);
set_LDI_CTRL_corlorbar_width(edc_base, 0x3C);
if (pinfo->type == PANEL_MIPI_CMD) {
set_LDI_CTRL_ldi_en(edc_base, K3_DISABLE);
} else {
set_LDI_CTRL_ldi_en(edc_base, K3_ENABLE);
}
set_LDI_INT_CLR(edc_base, 0xFFFFFFFF);
if (pinfo->type == PANEL_HDMI) {
/* dsi pixel off */
set_reg(edc_base + LDI_HDMI_DSI_GT, 0x1, 1, 0);
}
if (!(pinfo->bl_set_type & BL_SET_BY_PWM)) {
set_reg(edc_base + LDI_DE_SPACE_LOW, 0x1, 1, 1);
}
return 0;
}
static void prealloc_reg(struct brw_wm_compile *c)
{
int i, j;
struct brw_reg reg;
int nr_interp_regs = 0;
GLuint inputs = FRAG_BIT_WPOS | c->fp_interp_emitted | c->fp_deriv_emitted;
for (i = 0; i < 4; i++) {
reg = (i < c->key.nr_depth_regs)
? brw_vec8_grf(i*2, 0) : brw_vec8_grf(0, 0);
set_reg(c, PROGRAM_PAYLOAD, PAYLOAD_DEPTH, i, reg);
}
c->reg_index += 2*c->key.nr_depth_regs;
{
int nr_params = c->fp->program.Base.Parameters->NumParameters;
struct gl_program_parameter_list *plist =
c->fp->program.Base.Parameters;
int index = 0;
c->prog_data.nr_params = 4*nr_params;
for (i = 0; i < nr_params; i++) {
for (j = 0; j < 4; j++, index++) {
reg = brw_vec1_grf(c->reg_index + index/8,
index%8);
c->prog_data.param[index] =
&plist->ParameterValues[i][j];
set_reg(c, PROGRAM_STATE_VAR, i, j, reg);
}
}
c->nr_creg = 2*((4*nr_params+15)/16);
c->reg_index += c->nr_creg;
}
for (i = 0; i < FRAG_ATTRIB_MAX; i++) {
if (inputs & (1<<i)) {
nr_interp_regs++;
reg = brw_vec8_grf(c->reg_index, 0);
for (j = 0; j < 4; j++)
set_reg(c, PROGRAM_PAYLOAD, i, j, reg);
c->reg_index += 2;
}
}
c->prog_data.first_curbe_grf = c->key.nr_depth_regs * 2;
c->prog_data.urb_read_length = nr_interp_regs * 2;
c->prog_data.curb_read_length = c->nr_creg;
c->emit_mask_reg = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0);
c->reg_index++;
c->stack = brw_uw16_reg(BRW_GENERAL_REGISTER_FILE, c->reg_index, 0);
c->reg_index += 2;
}
/*
* Set task register contents
*/
SYSCALL ER _tk_set_reg( ID tskid,
T_REGS *pk_regs, T_EIT *pk_eit, T_CREGS *pk_cregs )
{
TCB *tcb;
ER ercd = E_OK;
CHECK_INTSK();
CHECK_TSKID(tskid);
CHECK_NONSELF(tskid);
tcb = get_tcb(tskid);
BEGIN_CRITICAL_SECTION;
if ( tcb->state == TS_NONEXIST ) {
ercd = E_NOEXS;
} else {
ercd = mp_check_domain_and_protection(tskid, tcb->tskid, tcb->tskatr);
if ( ercd == E_OK ) {
if ( is_ctxtsk(tcb) ) {
ercd = E_OBJ;
} else {
set_reg(tcb, pk_regs, pk_eit, pk_cregs);
}
}
}
END_CRITICAL_NO_DISPATCH;
return ercd;
}
void hisi_dss_mctl_ov_set_ctl_dbg_reg(struct hisi_fb_data_type *hisifd, char __iomem *mctl_dgb)
{
if (hisifd == NULL) {
HISI_FB_ERR("hisifd is null");
return;
}
if (is_mipi_cmd_panel(hisifd) && (hisifd->ldi_data_gate_en == 1)) {
//open underflow clear
set_reg(mctl_dgb, 0x782620, 32, 0);
} else {
//open underflow clear
set_reg(mctl_dgb, 0x70A620, 32, 0);
//set_reg(mctl_dgb, 0xB02620, 32, 0);
}
}
static int
create_state_record_for (struct dwarf_cursor *c, dwarf_state_record_t *sr,
unw_word_t ip)
{
int i, ret;
assert (c->pi_valid);
memset (sr, 0, sizeof (*sr));
for (i = 0; i < DWARF_NUM_PRESERVED_REGS + 2; ++i)
set_reg (sr, i, DWARF_WHERE_SAME, 0);
switch (c->pi.format)
{
case UNW_INFO_FORMAT_TABLE:
case UNW_INFO_FORMAT_REMOTE_TABLE:
ret = parse_fde (c, ip, sr);
break;
case UNW_INFO_FORMAT_DYNAMIC:
ret = parse_dynamic (c, ip, sr);
break;
default:
Debug (1, "Unexpected unwind-info format %d\n", c->pi.format);
ret = -UNW_EINVAL;
}
return ret;
}
/*
* Set task register
*/
SYSCALL ER _td_set_reg( ID tskid, T_REGS *regs, T_EIT *eit, T_CREGS *cregs )
{
TCB *tcb;
ER ercd = E_OK;
CHECK_TSKID(tskid);
CHECK_NONSELF(tskid);
#if 0 /* (030206) This is not an error. Please ignore. */
if ( eit != NULL ) {
if ( (eit->sr & (SR_BL|SR_I(15))) != 0 ) {
return E_PAR;
}
}
#endif
tcb = get_tcb(tskid);
BEGIN_CRITICAL_SECTION;
if ( tcb->state == TS_NONEXIST ) {
ercd = E_NOEXS;
} else if ( !MP_CMP_DOMIDPART(tskid, tcb->tskid) ) {
ercd = E_NOEXS;
} else if ( is_ctxtsk(tcb) ) {
ercd = E_OBJ;
} else {
set_reg(tcb, regs, eit, cregs);
}
END_CRITICAL_NO_DISPATCH;
return ercd;
}
extern "C" void slv6_X_set_reg(SLv6_Processor *proc,
const SLv6_Condition cond,
const uint8_t d,
const uint32_t data) {
if (!ConditionPassed(&proc->cpsr,cond)) return;
set_reg(proc,d,data);
}
static void set_reg_mask(struct asill_s *A, int r, int mask, int v)
{
int nv = get_reg(A, r) & ~mask;
nv |= v;
set_reg(A, r, nv);
}
void disable_ldi(struct hisi_fb_data_type *hisifd)
{
char __iomem *dss_base = 0;
BUG_ON(hisifd == NULL);
dss_base = hisifd->dss_base;
if (hisifd->index == PRIMARY_PANEL_IDX) {
set_reg(dss_base + PDP_LDI_CTRL, 0, 1, 0);
} else if (hisifd->index == EXTERNAL_PANEL_IDX) {
set_reg(dss_base + SDP_LDI_CTRL, 0, 1, 0);
} else {
;
}
}
static struct brw_reg
get_reg(struct brw_wm_compile *c, int file, int index, int component, int nr, GLuint neg, GLuint abs)
{
struct brw_reg reg;
switch (file) {
case PROGRAM_STATE_VAR:
case PROGRAM_CONSTANT:
case PROGRAM_UNIFORM:
file = PROGRAM_STATE_VAR;
break;
case PROGRAM_UNDEFINED:
return brw_null_reg();
default:
break;
}
if(c->wm_regs[file][index][component].inited)
reg = c->wm_regs[file][index][component].reg;
else
reg = brw_vec8_grf(c->reg_index, 0);
if(!c->wm_regs[file][index][component].inited) {
set_reg(c, file, index, component, reg);
c->reg_index++;
}
if (neg & (1<< component)) {
reg = negate(reg);
}
if (abs)
reg = brw_abs(reg);
return reg;
}
int asill_set_xy(struct asill_s *A, uint16_t x, uint16_t y)
{
if (x + A->width > A->max_width) {
x = A->max_width - A->width;
}
if (y + A->height > A->max_height) {
y = A->max_height - A->height;
}
A->start_x = x;
A->start_y = y;
pthread_mutex_lock(&A->cmd_lock);
set_reg(A, MT9M034_Y_ADDR_START, 0x0002 + A->start_y);
set_reg(A, MT9M034_X_ADDR_START, A->start_x);
set_reg(A, MT9M034_Y_ADDR_END, 0x0002 + A->start_y + A->height -1);
set_reg(A, MT9M034_X_ADDR_END, A->start_x + A->width - 1);
pthread_mutex_unlock(&A->cmd_lock);
return 0;
}
int init_sys_struct(SysStruct *ss)
{
int i;
if(ss == NULL)
return 1;
for(i = 0; i < NUM_PROCS; i++)
set_reg(ss, i, SP_REG, 0);
return 0;
}
virtual void set_reg(sys_bus_addr addr, uint32_t data, uint32_t mask) {
uint32_t reg = get_reg(addr);
// clear all unselected bits in input data
data &= mask;
// clear all selects bits in reg and set according to input data
reg &= ~mask;
reg |= data;
set_reg(addr, reg);
}
static int mipi_dsi_on_sub1(struct hisi_fb_data_type *hisifd, char __iomem *mipi_dsi_base)
{
BUG_ON(mipi_dsi_base == NULL);
/* mipi init */
mipi_init(hisifd, mipi_dsi_base);
/* switch to cmd mode */
set_reg(mipi_dsi_base + MIPIDSI_MODE_CFG_OFFSET, 0x1, 1, 0);
/* cmd mode: low power mode */
set_reg(mipi_dsi_base + MIPIDSI_CMD_MODE_CFG_OFFSET, 0x7f, 7, 8);
set_reg(mipi_dsi_base + MIPIDSI_CMD_MODE_CFG_OFFSET, 0xf, 4, 16);
set_reg(mipi_dsi_base + MIPIDSI_CMD_MODE_CFG_OFFSET, 0x1, 1, 24);
/* disable generate High Speed clock */
/* delete? */
set_reg(mipi_dsi_base + MIPIDSI_LPCLK_CTRL_OFFSET, 0x0, 1, 0);
return 0;
}
// TODO(amidvidy): Possibly remove references to obj. Not sure what this is actually for
void GRIProcessThread::Init(QObject* obj, ProcessDetails* proc_detail,
GRIRegulator *regulator) {
setParent(obj);
set_reg(regulator);
if (proc_detail) {
is_daq_ = proc_detail->isDaq;
set_name(proc_detail->name);
xml_path_ = proc_detail->xml_path;
}
}
void lapic_enable() {
// set bit 11 in the APIC_BASE MSR to enable the APIC
uint32_t base = msr_read(MSR_APIC_BASE);
base |= 1<<11;
msr_write(MSR_APIC_BASE, base);
// set the software-enable bit (8) in the spurious vector
set_reg(LAPIC_REG_SPURIOUS,
get_reg(LAPIC_REG_SPURIOUS) | (1<<8));
}
void enable_clk_panel(struct hisi_fb_data_type *hisifd)
{
char __iomem *dss_base = NULL;
uint32_t val = 0;
int prev_refcount = 0;
BUG_ON(hisifd == NULL);
dss_base = hisifd->dss_base;
down(&hisi_fb_dss_panel_clk_sem);
prev_refcount = panel_refcount++;
if (!prev_refcount) {
/* de-reset status */
val =0x0;
if (is_mipi_panel(hisifd)) {
val |= PDP_DSI0_DIS_RST_CFG;
}
if (is_dual_mipi_panel(hisifd)) {
val |= PDP_DSI1_DIS_RST_CFG;
}
outp32(dss_base + DSS_GLB_DIS_RST_CFG, val);
/* enable clk */
val = 0x0;
if (is_mipi_panel(hisifd)) {
val |= PDP_DSI0_EN_CLK_CFG;
}
if (is_dual_mipi_panel(hisifd)) {
val |= PDP_DSI1_EN_CLK_CFG;
if (is_ifbc_panel(hisifd)) {
set_reg(dss_base + DSS_GLB_PXL0_DIV, 0xb, 4, 0);
} else {
set_reg(dss_base + DSS_GLB_PXL0_DIV, 0x9, 4, 0);
}
}
if (is_ifbc_panel(hisifd)) {
val |= PDP_IFBC_EN_CLK_CFG;
}
outp32(dss_base + DSS_GLB_EN_CLK_CFG, val);
}
up(&hisi_fb_dss_panel_clk_sem);
}
/*******************************************************************************
** handle isr
*/
irqreturn_t dss_pdp_isr(int irq, void *ptr)
{
struct hisi_fb_data_type *hisifd = NULL;
uint32_t isr_s1 = 0;
uint32_t mask = 0;
hisifd = (struct hisi_fb_data_type *)ptr;
BUG_ON(hisifd == NULL);
isr_s1 = inp32(hisifd->dss_base + GLB_CPU_PDP_INTS);
outp32(hisifd->dss_base + GLB_CPU_PDP_INTS, ~0);
if (isr_s1 & BIT_VACTIVE0_START) {
if (hisifd->ov_vactive0_start_isr_handler)
hisifd->ov_vactive0_start_isr_handler(hisifd);
}
if (isr_s1 & BIT_VSYNC) {
if (hisifd->vsync_isr_handler) {
hisifd->vsync_isr_handler(hisifd);
}
if (g_enable_ovl_optimized) {
if (hisifd->ov_optimized)
hisifd->ov_optimized(hisifd, DSS_OVL0);
}
if (hisifd->buf_sync_signal) {
hisifd->buf_sync_signal(hisifd);
}
}
if (isr_s1 & BIT_BACKLIGHT) {
if (hisifd->sbl_isr_handler) {
hisifd->sbl_isr_handler(hisifd);
}
}
if (isr_s1 & BIT_LDI_UNFLOW) {
if (g_debug_ldi_underflow) {
/* ldi disable */
set_reg(hisifd->dss_base + DSS_LDI0_OFFSET + LDI_CTRL, 0, 1, 0);
}
mask = inp32(hisifd->dss_base + GLB_CPU_PDP_INT_MSK);
mask |= BIT_LDI_UNFLOW;
outp32(hisifd->dss_base + GLB_CPU_PDP_INT_MSK, mask);
HISI_FB_ERR("ldi underflow!\n");
}
return IRQ_HANDLED;
}
static int jdi_set_ct_cscValue(struct k3_fb_data_type *k3fd)
{
u32 edc_base = 0;
edc_base = k3fd->edc_base;
down(&ct_sem);
if (1 == g_is_csc_set) {
set_reg(edc_base + 0x400, 0x1, 1, 27);
set_reg(edc_base + 0x408, g_csc_value[0], 13, 0);
set_reg(edc_base + 0x408, g_csc_value[1], 13, 16);
set_reg(edc_base + 0x40C, g_csc_value[2], 13, 0);
set_reg(edc_base + 0x40C, g_csc_value[3], 13, 16);
set_reg(edc_base + 0x410, g_csc_value[4], 13, 0);
set_reg(edc_base + 0x410, g_csc_value[5], 13, 16);
set_reg(edc_base + 0x414, g_csc_value[6], 13, 0);
set_reg(edc_base + 0x414, g_csc_value[7], 13, 16);
set_reg(edc_base + 0x418, g_csc_value[8], 13, 0);
}
up(&ct_sem);
return 0;
}
static bool try_pop_registers(const memory_t* memory, unwind_state_t* state, uint32_t mask) {
uint32_t sp = state->gregs[R_SP];
bool sp_updated = false;
for (int i = 0; i < 16; i++) {
if (mask & (1 << i)) {
uint32_t value;
if (!try_get_word(memory, sp, &value)) {
return false;
}
if (i == R_SP) {
sp_updated = true;
}
set_reg(state, i, value);
sp += 4;
}
}
if (!sp_updated) {
set_reg(state, R_SP, sp);
}
return true;
}
