static void __init graphicsmaster_init_irq(void) { int irq; /* First the standard SA1100 IRQs */ sa1100_init_irq(); /* disable all IRQs */ ADS_INT_EN1 = 0; ADS_INT_EN2 = 0; /* clear all IRQs */ ADS_INT_ST1 = 0xff; ADS_INT_ST2 = 0xff; for (irq = IRQ_GRAPHICSMASTER_START; irq < IRQ_GRAPHICSMASTER_UCB1200; irq++) { irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; irq_desc[irq].mask_ack = ADS_mask_and_ack_irq0; irq_desc[irq].mask = ADS_mask_irq0; irq_desc[irq].unmask = ADS_unmask_irq0; } for (irq = IRQ_GRAPHICSMASTER_UCB1200; irq < IRQ_GRAPHICSMASTER_END; irq++) { irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; irq_desc[irq].mask_ack = ADS_mask_and_ack_irq1; irq_desc[irq].mask = ADS_mask_irq1; irq_desc[irq].unmask = ADS_unmask_irq1; } GPDR &= ~GPIO_GPIO0; set_GPIO_IRQ_edge(GPIO_GPIO0, GPIO_FALLING_EDGE); setup_arm_irq( IRQ_GPIO0, &ADS_ext_irq ); }
void __init ixdp2800_init_irq(void) { int i = 0; *IXDP2800_CPLD_INT_MASK = 0; /* turn off interrupts */ /* initialize chip specific interrupts */ ixp2000_init_irq(); /* * Slave only has NIC routed to it, so we don't init everything */ if (npu_is_master()) { for(i = NR_IXP2000_IRQS; i < NR_IXDP2800_IRQS; i++) { irq_desc[i].valid = 1; irq_desc[i].probe_ok = 0; irq_desc[i].mask_ack = ext_irq_mask; irq_desc[i].mask = ext_irq_mask; irq_desc[i].unmask = ext_irq_unmask; } /* init PCI interrupts */ setup_arm_irq(IRQ_IXP2000_PCIB, &ext_irq); } }
void __init irq_init_irq(void) { unsigned int irq; for (irq = 0; irq < NR_IRQS; irq++) { switch (irq) { case IRQ_UART0: case IRQ_UART1: case IRQ_UART2: case IRQ_TICK: case IRQ_CODEC: case IRQ_UART4: case IRQ_TOUCHSCREEN: case IRQ_UART3: case IRQ_FIFO: case IRQ_CAN: case IRQ_COMPACTFLASH: case IRQ_BOSH: case IRQ_ANAKIN: irq_desc[irq].valid = 1; irq_desc[irq].mask_ack = anakin_mask_irq; irq_desc[irq].mask = anakin_mask_irq; irq_desc[irq].unmask = anakin_unmask_irq; } } setup_arm_irq(IRQ_ANAKIN, &anakin_irq); }
static void __init system3_init_irq(void) { int irq; DPRINTK( "%s\n", "START" ); /* SA1111 IRQ not routed to a GPIO. */ sa1111_init_irq(-1); /* setup extra IRQs */ irq = IRQ_SYSTEM3_SMC9196; irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; #if 0 /* Highspeed Serial Bus not yet used */ irq = PT_USAR_IRQ; irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; #endif /* IRQ by CPLD */ set_GPIO_IRQ_edge( GPIO_GPIO(25), GPIO_RISING_EDGE ); setup_arm_irq( IRQ_GPIO25, &system3_irq ); }
/* * We only do anything if we are the master NPU on the board. * The slave NPU only has the ethernet chip going directly to * the PCIB interrupt input. */ void __init ixdp2400_init_irq(void) { int i = 0; /* initialize chip specific interrupts */ ixp2000_init_irq(); if (npu_is_master()) { /* Disable all CPLD interrupts */ acquire_slowport(&slowport_cpld_cfg); *IXDP2400_CPLD_INT_MASK = 0xff; release_slowport(); for(i = NR_IXP2000_IRQS; i < NR_IXDP2400_IRQS; i++) { irq_desc[i].valid = 1; irq_desc[i].probe_ok = 0; irq_desc[i].mask_ack = ext_irq_mask; irq_desc[i].mask = ext_irq_mask; irq_desc[i].unmask = ext_irq_unmask; } /* Hook into PCI interrupts */ setup_arm_irq(IRQ_IXP2000_PCIB, &ext_irq); } }
static void __init graphicsmaster_init_irq(void) { int irq; /* First the standard SA1100 IRQs */ sa1100_init_irq(); /* disable all IRQs */ ADS_INT_EN1 = 0; ADS_INT_EN2 = 0; /* clear all IRQs */ ADS_INT_ST1 = 0xff; ADS_INT_ST2 = 0xff; for (irq = ADS_EXT_IRQ(0); irq <= ADS_EXT_IRQ(7); irq++) { irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; irq_desc[irq].mask_ack = ADS_mask_and_ack_irq0; irq_desc[irq].mask = ADS_mask_irq0; irq_desc[irq].unmask = ADS_unmask_irq0; } for (irq = ADS_EXT_IRQ(8); irq <= ADS_EXT_IRQ(15); irq++) { irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; irq_desc[irq].mask_ack = ADS_mask_and_ack_irq1; irq_desc[irq].mask = ADS_mask_irq1; irq_desc[irq].unmask = ADS_unmask_irq1; } set_GPIO_IRQ_edge(GPIO_GPIO0, GPIO_FALLING_EDGE); setup_arm_irq( IRQ_GPIO0, &ADS_ext_irq ); }
__initfunc(void time_init(void)) { xtime.tv_sec = setup_timer(); xtime.tv_usec = 0; setup_arm_irq(IRQ_TIMER, &irqtimer); }
void dm270_setup_timer(struct irqaction *timer_irq) { u_int16_t reg; /* Configure timer.c so that dm270_gettimeoffset will be used * to get the elapsed microseconds between interrupts. */ gettimeoffset = dm270_gettimeoffset; /* Capture the interrupt through dm270_timer_interrupt */ timer_irq->handler = dm270_timer_interrupt; setup_arm_irq(IRQ_TIMER, timer_irq); /* Start the general purpose timer 0 running in auto-reload mode * so that an interrupt is generated at the rate of HZ (param.h) * which typically is set to 100HZ. * When HZ is set to 100 then COUNTS_PER_INTERRUPT should be * established to reflect timer counts that occur every 10ms * (giving you 100 of them per second -- 100HZ). DM270's clock * is 87.75MHz and we're using a timer prescalar divide value * of 350 (350 == divide input clock frequency by 351) which then * yields a 16 bit COUNTS_PER_INTERRUPT value of 2500. Prescaler * divide value is chosen as 350 since DM270's clock is an * integer multiple of 351. */ /* Disable clock to timer 0 */ reg = inw(DM270_CLKC_MOD2); outw((reg & ~(DM270_CLKC_MOD2_RSV_MASK | DM270_CLKC_MOD2_CTMR0)), DM270_CLKC_MOD2); /* Select CLK_ARM as timer 0 clock source */ reg = inw(DM270_CLKC_CLKC); outw((reg & ~(DM270_CLKC_CLKC_CTM0S)), DM270_CLKC_CLKC); /* Enable clock to timer 0 */ reg = inw(DM270_CLKC_MOD2); reg &= ~(DM270_CLKC_MOD2_RSV_MASK); outw((reg | DM270_CLKC_MOD2_CTMR0), DM270_CLKC_MOD2); /* Stop timer 0 */ reg = inw(DM270_TMR0_TMMD); outw((reg & ~(DM270_TMR_TMMD_MODE_MASK | DM270_TMR_TMMD_TEST_MASK | DM270_TMR_TMMD_RSV_MASK)), DM270_TMR0_TMMD); /* Wait till timer 0 stops??? */ /* Set timer 0 counter */ outw(((CONFIG_DM270_TIMER_PRESCALE - 1) & DM270_TMR_TMPRSCL_PRSCL_MASK), DM270_TMR0_TMPRSCL); outw((u_int16_t)((COUNTS_PER_INTERRUPT - 1) & 0xffff), DM270_TMR0_TMVAL); /* Set free run mode for timer 0 */ reg = inw(DM270_TMR0_TMMD); reg &= ~(DM270_TMR_TMMD_MODE_MASK | DM270_TMR_TMMD_TEST_MASK | DM270_TMR_TMMD_RSV_MASK); outw((reg | DM270_TMR_TMMD_MODE_FREERUN), DM270_TMR0_TMMD); }
static int hr_timer_init(void) { int ret; volatile mputimer_regs_t * subhz_timer = mputimer_base(2); subhz_timer->cntl = 0; ret = setup_arm_irq(INT_TIMER3, &hr_timer_irq); return ret; }
static void __init neponset_init_irq(void) { sa1111_init_irq(-1); /* SA1111 IRQ not routed to a GPIO */ /* setup extra Neponset IRQs */ irq_desc[IRQ_NEPONSET_SMC9196].valid = 1; irq_desc[IRQ_NEPONSET_SMC9196].probe_ok = 1; irq_desc[IRQ_NEPONSET_USAR].valid = 1; irq_desc[IRQ_NEPONSET_USAR].probe_ok = 1; set_GPIO_IRQ_edge(GPIO_GPIO25, GPIO_RISING_EDGE); setup_arm_irq(IRQ_GPIO25, &neponset_irq); }
static void __init neponset_init_irq(void) { int irq; sa1111_init_irq(-1); /* SA1111 IRQ not routed to a GPIO */ /* setup extra Neponset IRQs */ irq = NEPONSET_ETHERNET_IRQ; irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; irq = NEPONSET_USAR_IRQ; irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 1; set_GPIO_IRQ_edge(ASSABET_GPIO_NEP_IRQ, GPIO_RISING_EDGE); setup_arm_irq(ASSABET_IRQ_GPIO_NEP_IRQ, &neponset_irq); }
void __init sa1111_init_irq(int irq_nr) { int irq; /* disable all IRQs */ INTEN0 = 0; INTEN1 = 0; /* * detect on rising edge. Note: Feb 2001 Errata for SA1111 * specifies that S0ReadyInt and S1ReadyInt should be '1'. */ INTPOL0 = 0; INTPOL1 = 1 << (S0_READY_NINT - SA1111_IRQ(32)) | 1 << (S1_READY_NINT - SA1111_IRQ(32)); /* clear all IRQs */ INTSTATCLR0 = -1; INTSTATCLR1 = -1; for (irq = SA1111_IRQ(0); irq <= SA1111_IRQ(26); irq++) { irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 0; irq_desc[irq].mask_ack = sa1111_mask_and_ack_lowirq; irq_desc[irq].mask = sa1111_mask_lowirq; irq_desc[irq].unmask = sa1111_unmask_lowirq; } for (irq = SA1111_IRQ(32); irq <= SA1111_IRQ(54); irq++) { irq_desc[irq].valid = 1; irq_desc[irq].probe_ok = 0; irq_desc[irq].mask_ack = sa1111_mask_and_ack_highirq; irq_desc[irq].mask = sa1111_mask_highirq; irq_desc[irq].unmask = sa1111_unmask_highirq; } /* Register SA1111 interrupt */ if (irq_nr >= 0) setup_arm_irq(irq_nr, &sa1111_irq); }