Esempio n. 1
0
static inline void setup_syscnt(void)
{
    struct gpt_device *dev = id_to_dev(GPT_SYSCNT_ID);

    setup_gpt_dev_locked(dev, GPT_FREE_RUN, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                0, NULL, 0);
}
Esempio n. 2
0
static inline void setup_syscnt(void)
{
    struct gpt_device *dev = id_to_dev(GPT_SYSCNT_ID);
	
#ifndef CONFIG_MT6582_FPGA

    setup_gpt_dev_locked(dev, GPT_FREE_RUN, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                0, NULL, 0);
#else
   //use div2 for 6Mhz
   setup_gpt_dev_locked(dev, GPT_FREE_RUN, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                0, NULL, 0);
#endif

    printk("fwq sysc count \n");
}
Esempio n. 3
0
static inline void setup_clksrc(u32 freq)
{
	struct clocksource *cs = &gpt_clocksource;
	struct gpt_device *dev = id_to_dev(GPT_CLKSRC_ID);
	struct timecounter *mt_timecounter;
	u64 start_count;

	pr_alert("setup_clksrc1: dev->base_addr=0x%lx GPT2_CON=0x%x\n",
		(unsigned long)dev->base_addr, __raw_readl(dev->base_addr));
	cs->mult = clocksource_hz2mult(freq, cs->shift);
	sched_clock_register(mt_read_sched_clock, 32, freq);

	setup_gpt_dev_locked(dev, GPT_FREE_RUN, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
		0, NULL, 0);

	clocksource_register(cs);

	start_count = mt_read_sched_clock();
	mt_cyclecounter.mult = cs->mult;
	mt_cyclecounter.shift = cs->shift;
	mt_timecounter = arch_timer_get_timecounter();
	timecounter_init(mt_timecounter, &mt_cyclecounter, start_count);
	pr_alert("setup_clksrc1: mt_cyclecounter.mult=0x%x mt_cyclecounter.shift=0x%x\n",
		mt_cyclecounter.mult, mt_cyclecounter.shift);
	pr_alert("setup_clksrc2: dev->base_addr=0x%lx GPT2_CON=0x%x\n",
		(unsigned long)dev->base_addr, __raw_readl(dev->base_addr));
}
Esempio n. 4
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static inline void setup_syscnt_assist(void)
{
    struct gpt_device *dev = id_to_dev(GPT_SYSCNT_ASSIST_ID);

    setup_gpt_dev_locked(dev, GPT_REPEAT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                0xFFFFFFFF, syscnt_assist_handler, GPT_ISR | GPT_NOAUTOEN);

    syscnt_assist_init_ops();
}
Esempio n. 5
0
static inline void setup_clksrc(void) 
{
    struct clocksource *cs = &mt6582_gpt.clocksource;
    struct gpt_device *dev = id_to_dev(GPT_CLKSRC_ID);

    cs->mult = clocksource_hz2mult(SYS_CLK_RATE, cs->shift);
#ifndef CONFIG_MT6582_FPGA

    setup_gpt_dev_locked(dev, GPT_FREE_RUN, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                0, NULL, 0);
#else

     setup_gpt_dev_locked(dev, GPT_FREE_RUN, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                0, NULL, 0);

#endif
	g_clksrc_init = 1;
}
Esempio n. 6
0
static inline void setup_clksrc(void)
{
    struct clocksource *cs = &mt6582_gpt.clocksource;
    struct gpt_device *dev = id_to_dev(GPT_CLKSRC_ID);

    cs->mult = clocksource_hz2mult(SYS_CLK_RATE, cs->shift);

    setup_gpt_dev_locked(dev, GPT_FREE_RUN, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                0, NULL, 0);
    sched_clock_register((void *)mt_read_sched_clock, 32, SYS_CLK_RATE);
}
Esempio n. 7
0
static inline void setup_clkevt(void)
{
    unsigned int cmp;
    struct clock_event_device *evt = &mt6582_gpt.clockevent;
    struct gpt_device *dev = id_to_dev(GPT_CLKEVT_ID);

    evt->mult = div_sc(SYS_CLK_RATE, NSEC_PER_SEC, evt->shift);
    evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
    evt->min_delta_ns = clockevent_delta2ns(3, evt);
    evt->cpumask = cpumask_of(0);
#ifndef CONFIG_MT6582_FPGA

    setup_gpt_dev_locked(dev, GPT_REPEAT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                SYS_CLK_RATE / HZ, clkevt_handler, GPT_ISR);
#else 
    setup_gpt_dev_locked(dev, GPT_REPEAT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                SYS_CLK_RATE / HZ, clkevt_handler, GPT_ISR);
#endif

    __gpt_get_cmp(dev, &cmp); 
    printk("GPT1_CMP = %d, HZ = %d\n", cmp, HZ);
}
static inline void setup_clksrc(void)
{
    struct clocksource *cs = &mt6582_gpt.clocksource;
    struct gpt_device *dev = id_to_dev(GPT_CLKSRC_ID);

    cs->mult = clocksource_hz2mult(SYS_CLK_RATE, cs->shift);

    setup_gpt_dev_locked(dev, GPT_FREE_RUN, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
                0, NULL, 0);
#if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0))
    setup_sched_clock_needs_suspend((void *)mt_read_sched_clock, 32, SYS_CLK_RATE);
#else
    setup_sched_clock((void *)mt_read_sched_clock, 32, SYS_CLK_RATE);
#endif
}
Esempio n. 9
0
static inline void setup_clkevt(u32 freq)
{
	unsigned int cmp;
	struct clock_event_device *evt = &gpt_clockevent;
	struct gpt_device *dev = id_to_dev(GPT_CLKEVT_ID);

	evt->mult = div_sc(freq, NSEC_PER_SEC, evt->shift);
	evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
	evt->min_delta_ns = clockevent_delta2ns(3, evt);
	evt->cpumask = cpumask_of(0);

	setup_gpt_dev_locked(dev, GPT_REPEAT, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1,
		freq / HZ, clkevt_handler, GPT_ISR);

	__gpt_get_cmp(dev, &cmp);
	pr_alert("GPT1_CMP = %d, HZ = %d\n", cmp, HZ);

	clockevents_register_device(evt);
}
Esempio n. 10
0
int request_gpt(unsigned int id, unsigned int mode, unsigned int clksrc, 
                unsigned int clkdiv, unsigned int cmp, 
                void (*func)(unsigned long), unsigned int flags)
{
    unsigned long save_flags;
    struct gpt_device *dev = id_to_dev(id);
    if (!dev)
        return -EINVAL;

    if (dev->flags & GPT_IN_USE) {
        printk(KERN_ERR "%s: GPT%d is in use!\n", __func__, (id + 1));
        return -EBUSY;
    }

    gpt_update_lock(save_flags);
    setup_gpt_dev_locked(dev, mode, clksrc, clkdiv, cmp, func, flags);
    gpt_update_unlock(save_flags);

    return 0;
}