void main(void)
{
struct puzzleStruct puzzle;
struct buttonStruct buttons;
bool result = true;
//init code here
setup_int();
init_puzzle(&puzzle);
init_buttons(&buttons);
init_inputs();
//Enter main loop
for(;;) {
//Draw GUI
build_gui(&puzzle);
//Handle USB
update_puzzle(&puzzle,&buttons);
//Set output
set_output(&puzzle);
//Check inputs
update_buttons(&buttons);
//Read result
result = check_result(&puzzle);
}
}
void
xf86ExecX86int10(xf86Int10InfoPtr pInt)
{
int sig = setup_int(pInt);
if (int_handler(pInt))
while(do_vm86(pInt)) {};
finish_int(pInt, sig);
}
u8 ISA_MODEM::read(unsigned nreg)
{
if (nreg < 2 && (reg[3] & 0x80)) return div[nreg];
u8 result = reg[nreg];
if (nreg == 0)
{ // read char from buffer
if (conf.mem_model == MM_ATM3)
result = 0;
if (rhead != rtail)
{
result = reg[0] = rcbuf[rtail++];
rtail &= (BSIZE-1);
}
if (rhead != rtail)
reg[5] |= 1;
else
reg[5] &= ~1;
setup_int();
}
if (nreg == 5)
{
reg[5] &= ~0x0E;
setup_int();
}
if (nreg == 6)
{
DWORD ModemStatus;
GetCommModemStatus(hPort, &ModemStatus);
u8 r6 = reg[6];
reg[6] &= ~(1 << 4);
reg[6] |= (ModemStatus & MS_CTS_ON) ? (1 << 4): 0;
reg[6] &= ~1;
reg[6] |= ((r6 ^ reg[6]) & (1 << 4)) >> 4;
result = reg[6];
}
USI
fr30_inte (SIM_CPU *current_cpu, PCADDR pc, int num)
{
/* The new pc is the trap #9 vector entry.
We assume there's a branch there to some handler. */
USI new_pc;
setup_int (current_cpu, pc);
fr30bf_h_ilm_set (current_cpu, 4);
new_pc = GETMEMSI (current_cpu, pc,
fr30bf_h_dr_get (current_cpu, H_DR_TBR)
+ 1024 - ((9 + 1) * 4));
return new_pc;
}
void
xf86ExecX86int10(xf86Int10InfoPtr pInt)
{
int sig = setup_int(pInt);
if (sig < 0)
return;
if (int_handler(pInt)) {
X86EMU_exec();
}
finish_int(pInt, sig);
}
void ISA_MODEM::io()
{
if (!hPort || hPort == INVALID_HANDLE_VALUE)
return;
unsigned char temp[BSIZE];
int needwrite = whead - wtail;
if (needwrite < 0)
needwrite += BSIZE;
if (needwrite)
{
if (whead > wtail)
memcpy(temp, wbuf+wtail, needwrite);
else
{
memcpy(temp, wbuf+wtail, BSIZE-wtail);
memcpy(temp+BSIZE-wtail, wbuf, whead);
}
DWORD written = 0;
if (WriteFile(hPort, temp, needwrite, &written, 0))
{
//printf("\nsend: "); dump1(temp, written);
wtail = (wtail+written) & (BSIZE-1);
}
}
if (((whead+1) & (BSIZE-1)) != wtail) reg[5] |= 0x60;
int canread = rtail - rhead - 1;
if (canread < 0)
canread += BSIZE;
if (canread)
{
DWORD read = 0;
if (ReadFile(hPort, temp, canread, &read, 0) && read)
{
for (unsigned i = 0; i < read; i++)
rcbuf[rhead++] = temp[i], rhead &= (BSIZE-1);
//printf("\nrecv: "); dump1(temp, read);
}
}
if (rhead != rtail)
reg[5] |= 1;
setup_int();
}
void ISA_MODEM::write(unsigned nreg, unsigned char value)
{
DCB dcb;
if ((1<<nreg) & ((1<<2)|(1<<5)|(1<<6))) return; // R/O registers
if (nreg < 2 && (reg[3] & 0x80))
{
div[nreg] = value;
if (GetCommState(hPort, &dcb))
{
if (!divfq) divfq = 1;
dcb.BaudRate = 115200 / divfq;
SetCommState(hPort, &dcb);
}
return;
}
if (nreg == 0)
{ // write char to output buffer
reg[5] &= ~0x60;
if (((whead+1) & (BSIZE-1)) == wtail)
{
reg[5] |= 2;
}
else
{
wbuf[whead++] = value, whead &= (BSIZE-1);
if (((whead+1) & (BSIZE-1)) != wtail) reg[5] |= 0x60;
}
setup_int();
return;
}
reg[nreg] = value;
// Thu 28 Jul 2005. transfer mode control (code by Alex/AT)
if (nreg == 3)
{
// LCR set, renew modem config
if (!GetCommState(hPort, &dcb)) return;
dcb.fBinary = TRUE;
dcb.fParity = (reg[3] & 8)? TRUE : FALSE;
// dcb.fParity = FALSE; // fix suggested by lvd
dcb.fOutxCtsFlow = FALSE;
dcb.fOutxDsrFlow = FALSE;
dcb.fDtrControl = DTR_CONTROL_DISABLE;
dcb.fDsrSensitivity = FALSE;
dcb.fTXContinueOnXoff = FALSE;
dcb.fOutX = FALSE;
dcb.fInX = FALSE;
dcb.fErrorChar = FALSE;
dcb.fNull = FALSE;
dcb.fRtsControl = RTS_CONTROL_DISABLE;
dcb.fAbortOnError = FALSE;
// dcb.ByteSize = 6 + (reg[3] & 2) - (reg[3] & 1);
// dcb.ByteSize = 8; // fix suggested by lvd
dcb.ByteSize = 5 + (reg[3] & 3); // fix by Deathsoft
static const BYTE parity[] = { ODDPARITY, EVENPARITY, MARKPARITY, SPACEPARITY };
dcb.Parity = (reg[3] & 8)? parity[(reg[3]>>4) & 3] : NOPARITY;
if (!(reg[3] & 4)) dcb.StopBits = ONESTOPBIT;
else dcb.StopBits = ((reg[3] & 3) == 1)? ONE5STOPBITS : TWOSTOPBITS;
SetCommState(hPort, &dcb);
return;
}
if (nreg == 4)
{
// MCR set, renew DTR/RTS
EscapeCommFunction(hPort, (reg[4] & 1)? SETDTR : CLRDTR);
EscapeCommFunction(hPort, (reg[4] & 2)? SETRTS : CLRRTS);
}
}
int main()
{
long int delay;
int brg;
// Call the various initialization functions.
init_osd();
setup_pll();
setup_io();
setup_int();
init_gfx(1);
// Turn on doze, with a 1:1 ratio.
CLKDIVbits.DOZEN = 0;
CLKDIVbits.DOZE = 0b000;
// Start in console mode. Print startup messages.
con_init();
con_rolling = 0;
con_puts("Super OSD v3.2-lite", 0);
con_puts("dsPIC33F side", 0);
con_puts("Copr. 2010 Tom O.", 0); ;
con_puts("COMPILED FOR: ENGLISH", 0);
con_puts("", 0);
con_puts("Booting kernel [ OK ]", 0);
con_puts("Verify 24F [ OK ]", 0);
con_puts("Verify 33F [ OK ]", 0);
con_puts("Switch to hi res [ OK ]", 0);
init_gfx(0);
if(mem_test_full())
{
con_puts("VRAM test [ OK ]", 0);
}
else
{
con_puts("VRAM test [FAIL]", 0);
con_puts("Check memory soon! ", 0);
// Show warning for some time
delay = 2000000;
while(delay--);
}
// Clear graphics buffers of any memory test data remaining.
init_gfx(0);
con_puts("Init UART [ OK ]", 0);
// BUG: occasionally resets processor on start up
//interface_init_uart();
//brg = interface_set_baudrate(1843200);
//sprintf(temp, "BRG=%d", brg);
//con_puts(temp, 0);
/*
con_puts("PC detect... [FAIL]", 0);
con_puts("GPS detect... [ OK ]", 0);
con_puts("SPI initialized [ OK ]", 0);
con_puts("Found flash mem [ OK ]", 0);
con_puts(" Size: 2048 KB [ OK ]", 0);
con_puts("USB not supported [SKIP]", 0);
con_puts("Init GPS [ OK ]", 0);
con_puts("Test I2C [ OK ]", 0);
con_puts(" Xbee Adap. 2.0 [ OK ]", 0);
con_puts(" LSM303 acc [ OK ]", 0);
con_puts(" LSM303 mag [ OK ]", 0);
con_puts(" ITG3200 gyro [FAIL]", 0);
con_puts("Loading settings [ OK ]", 0);
con_puts("Init splash [ OK ]", 0);
*/
// Demo HUD.
//buffer_mode(0);
con_puts("Launching hud_demo", 0);
delayhowlong = 10000;
hud_demo();
}
void ZF232::write(u8 nreg, u8 value)
{
if (nreg >= 0xF8)
{
nreg &= 0x07;
DCB dcb;
if ((nreg == 5) || (nreg == 6))
return; // R/O registers
if (nreg < 2 && (rs_reg[3] & 0x80))
{
rs_div[nreg] = value;
if (rs_hPort && rs_hPort != INVALID_HANDLE_VALUE && GetCommState(rs_hPort, &dcb))
{
if (!rs_divfq)
dcb.BaudRate = 230400; // non standard baurrate
else
dcb.BaudRate = 115200 / rs_divfq;
SetCommState(rs_hPort, &dcb);
}
return;
}
if (nreg == 0)
{ // THR, write char to output buffer
rs_reg[5] &= ~0x60;
if (((rs_whead + 1) & RS_TXBMASK) != rs_wtail)
{
rs_wbuf[rs_whead++] = value;
rs_whead &= RS_TXBMASK;
if (((rs_whead + 1) & RS_TXBMASK) != rs_wtail)
rs_reg[5] |= 0x60; // Transmitter holding register empty | transmitter empty
}
else
{
// printf("write to full FIFO\n");
// rs_reg[5] |= 2; Overrun error (Ошибка, этот бит только на прием, а не на передачу)
}
setup_int();
return;
}
if (nreg == 2) // FCR
{
ULONG Flags = 0;
if (value & 2) // RX FIFO reset
{
rs_rhead = rs_rtail = 0;
Flags |= PURGE_RXCLEAR | PURGE_RXABORT;
}
if (value & 4) // TX FIFO reset
{
rs_whead = rs_wtail = 0;
Flags |= PURGE_TXCLEAR | PURGE_TXABORT;
}
if (Flags)
PurgeComm(rs_hPort, Flags);
return;
}
u8 old = rs_reg[nreg];
rs_reg[nreg] = value;
if (nreg == 3 && rs_hPort && rs_hPort != INVALID_HANDLE_VALUE)
{
// LCR set, renew modem config
if (!GetCommState(rs_hPort, &dcb))
return;
dcb.fBinary = TRUE;
dcb.fParity = (rs_reg[3] & 8) ? TRUE : FALSE;
dcb.fOutxCtsFlow = FALSE;
dcb.fOutxDsrFlow = FALSE;
dcb.fDtrControl = DTR_CONTROL_DISABLE;
dcb.fDsrSensitivity = FALSE;
dcb.fTXContinueOnXoff = FALSE;
dcb.fOutX = FALSE;
dcb.fInX = FALSE;
dcb.fErrorChar = FALSE;
dcb.fNull = FALSE;
dcb.fRtsControl = RTS_CONTROL_DISABLE;
dcb.fAbortOnError = FALSE;
dcb.ByteSize = 5 + (rs_reg[3] & 3); // fix by Deathsoft
static const BYTE parity[] = { ODDPARITY, EVENPARITY, MARKPARITY, SPACEPARITY };
dcb.Parity = (rs_reg[3] & 8) ? parity[(rs_reg[3] >> 4) & 3] : NOPARITY;
if (!(rs_reg[3] & 4))
dcb.StopBits = ONESTOPBIT;
else
dcb.StopBits = ((rs_reg[3] & 3) == 1) ? ONE5STOPBITS : TWOSTOPBITS;
SetCommState(rs_hPort, &dcb);
return;
}
if (nreg == 4 && rs_hPort && rs_hPort != INVALID_HANDLE_VALUE)
{
// MCR set, renew DTR/RTS
if ((old ^ rs_reg[4]) & 0x20) // auto rts/cts toggled
{
if (!GetCommState(rs_hPort, &dcb))
return;
if (rs_reg[4] & 0x20) // auto rts/cts enabled
{
dcb.fOutxCtsFlow = TRUE;
dcb.fRtsControl = RTS_CONTROL_HANDSHAKE;
}
else // auto rts/cts disabled
{
dcb.fOutxCtsFlow = FALSE;
dcb.fRtsControl = RTS_CONTROL_DISABLE;
}
SetCommState(rs_hPort, &dcb);
}
if (!(rs_reg[4] & 0x20)) // auto rts/cts disabled
{
if ((old ^ rs_reg[4]) & 1)
{
EscapeCommFunction(rs_hPort, (rs_reg[4] & 1) ? SETDTR : CLRDTR);
}
if ((old ^ rs_reg[4]) & 2)
{
EscapeCommFunction(rs_hPort, (rs_reg[4] & 2) ? SETRTS : CLRRTS);
}
}
}
}
void ZF232::io()
{
//- - -
if (rs_hPort && rs_hPort != INVALID_HANDLE_VALUE)
{
{
static u8 tempwr[WOVBSIZE];
static DWORD written;
if (WaitForSingleObject(rs_OvW.hEvent, 0) == WAIT_OBJECT_0)
{
written = rs_OvW.InternalHigh;
rs_OvW.InternalHigh = 0;
rs_wtail = (rs_wtail + written) & RS_TXBMASK;
//if (written) printf("rs write %u bytes\n", written);
DWORD needwrite = (rs_whead - rs_wtail) & RS_TXBMASK;
if (needwrite)
{
if (needwrite > WOVBSIZE)
needwrite = WOVBSIZE;
unsigned j = rs_wtail;
for (unsigned i = 0; i < needwrite; i++)
{
tempwr[i] = rs_wbuf[j++];
j &= RS_TXBMASK;
}
WriteFile(rs_hPort, tempwr, needwrite, &written, &rs_OvW);
}
}
}
if (((rs_whead + 1) & RS_RXBMASK) != rs_wtail)
rs_reg[5] |= 0x60;
{
static u8 temprd[ROVBSIZE];
static DWORD readed;
if (WaitForSingleObject(rs_OvR.hEvent, 0) == WAIT_OBJECT_0)
{
readed = rs_OvR.InternalHigh;
rs_OvR.InternalHigh = 0;
if (readed)
{
//printf("rs read %u byted\n", readed);
for (unsigned i = 0; i < readed; i++)
{
rs_rcbuf[rs_rhead++] = temprd[i];
rs_rhead &= RS_RXBMASK;
}
}
DWORD canread = (rs_rtail - rs_rhead - 1) & RS_RXBMASK;
if (canread)
{
if (canread > ROVBSIZE)
canread = ROVBSIZE;
ReadFile(rs_hPort, temprd, canread, &readed, &rs_OvR);
}
}
}
if (rs_rhead != rs_rtail)
rs_reg[5] |= 1;
setup_int();
}
//- - -
if (zf_hPort && zf_hPort != INVALID_HANDLE_VALUE)
{
{
static u8 tempwr[WOVBSIZE];
static DWORD written;
if (WaitForSingleObject(zf_OvW.hEvent, 0) == WAIT_OBJECT_0)
{
written = zf_OvW.InternalHigh;
zf_OvW.InternalHigh = 0;
zf_wtail = (zf_wtail + written) & ZF_TXBMASK;
//if (written) printf("zf write %u bytes\n", written);
DWORD needwrite = (zf_whead - zf_wtail) & ZF_TXBMASK;
if (needwrite)
{
if (needwrite > WOVBSIZE)
needwrite = WOVBSIZE;
unsigned j = zf_wtail;
for (unsigned i = 0; i < needwrite; i++)
{
tempwr[i] = zf_wbuf[j++];
j &= ZF_TXBMASK;
}
WriteFile(zf_hPort, tempwr, needwrite, &written, &zf_OvW);
}
}
}
{
static u8 temprd[ROVBSIZE];
static DWORD readed;
if (WaitForSingleObject(zf_OvR.hEvent, 0) == WAIT_OBJECT_0)
{
readed = zf_OvR.InternalHigh;
zf_OvR.InternalHigh = 0;
if (readed)
{
//printf("zf read %u byted\n", readed);
for (unsigned i = 0; i < readed; i++)
{
zf_rcbuf[zf_rhead++] = temprd[i];
zf_rhead &= ZF_RXBMASK;
}
}
int canread = (zf_rtail - zf_rhead - 1) & ZF_RXBMASK;
if (canread)
{
if (canread > ROVBSIZE)
canread = ROVBSIZE;
ReadFile(zf_hPort, temprd, canread, &readed, &zf_OvR);
}
}
}
}
//- - -
}
int
main(void)
{
unsigned char idle = 0;
// the crt has disabled interrupts before main is called
// z88dk tracks the border colour so that beeper audio does not change the border colour while playing.
// (this project contains a 3rd party ntropic player that does not obey z88dk convention so we set the border to same colour)
zx_border(INK_BLACK);
// set up the block memory allocator with one queue
// max size requested by sp1 will be 24 bytes or block size of 25 (+1 for overhead)
balloc_reset(0); // make queue 0 empty
balloc_addmem(0, sizeof(block_of_ram)/25, 24, block_of_ram); // add free memory from bss section
balloc_addmem(0, 8, 24, (void *)0xd101); // another eight from an unused area
// interrupt mode 2
setup_int();
// sp1.lib
sp1_Initialize(SP1_IFLAG_MAKE_ROTTBL | SP1_IFLAG_OVERWRITE_TILES | SP1_IFLAG_OVERWRITE_DFILE, INK_BLACK | PAPER_BLACK, ' ');
// sp1_Validate(&cr); // not necessary since sp1_Initialize will not mark screen for update
ps0.bounds = &cr;
ps0.flags = SP1_PSSFLAG_INVALIDATE;
ps0.visit = 0;
intrinsic_ei();
// setup our font
pt = font;
for (i = 0; i < 96; ++i, pt += 8)
sp1_TileEntry(32 + i, pt);
// setup the bg tiles
pt = tiles;
for (i = 0; i < TILES_LEN; ++i, pt += 8)
sp1_TileEntry(TILES_BASE + i, pt);
init_sprites();
draw_menu();
srand(tick); // 256 different games are possible
while(1)
{
key = in_inkey();
if (key)
{
if (key == '4')
{
playfx(FX_SELECT);
in_wait_nokey();
run_redefine_keys();
idle = 0;
draw_menu();
}
if (key == '1' || key == '2' || key == '3')
{
playfx(FX_SELECT);
joy_k.left = in_key_scancode(keys[0]);
joy_k.right = in_key_scancode(keys[1]);
// we don't use up/down in this game
joy_k.down = in_key_scancode(keys[0]);
joy_k.up = in_key_scancode(keys[1]);
joy_k.fire = in_key_scancode(keys[2]);
if (key == '1')
joyfunc = (JOYFUNC)in_stick_keyboard;
if (key == '2')
joyfunc = (JOYFUNC)in_stick_kempston;
if (key == '3')
joyfunc = (JOYFUNC)in_stick_sinclair1;
// run game
run_intro();
run_play();
idle = 0;
draw_menu();
}
}
if (idle++ == 255)
{
// go back to the welcome screen after a while
// if the player doesn't do anything
idle = 0;
draw_menu();
}
wait();
sp1_UpdateNow();
}
}
USI
fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num)
{
SIM_DESC sd = CPU_STATE (current_cpu);
host_callback *cb = STATE_CALLBACK (sd);
#ifdef SIM_HAVE_BREAKPOINTS
/* Check for breakpoints "owned" by the simulator first, regardless
of --environment. */
if (num == TRAP_BREAKPOINT)
{
/* First try sim-break.c. If it's a breakpoint the simulator "owns"
it doesn't return. Otherwise it returns and let's us try. */
sim_handle_breakpoint (sd, current_cpu, pc);
/* Fall through. */
}
#endif
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
{
/* The new pc is the trap vector entry.
We assume there's a branch there to some handler. */
USI new_pc;
setup_int (current_cpu, pc);
fr30bf_h_ibit_set (current_cpu, 0);
new_pc = GETMEMSI (current_cpu, pc,
fr30bf_h_dr_get (current_cpu, H_DR_TBR)
+ 1024 - ((num + 1) * 4));
return new_pc;
}
switch (num)
{
case TRAP_SYSCALL :
{
/* TODO: find out what the ABI for this is */
CB_SYSCALL s;
CB_SYSCALL_INIT (&s);
s.func = fr30bf_h_gr_get (current_cpu, 0);
s.arg1 = fr30bf_h_gr_get (current_cpu, 4);
s.arg2 = fr30bf_h_gr_get (current_cpu, 5);
s.arg3 = fr30bf_h_gr_get (current_cpu, 6);
if (s.func == TARGET_SYS_exit)
{
sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
}
s.p1 = (PTR) sd;
s.p2 = (PTR) current_cpu;
s.read_mem = syscall_read_mem;
s.write_mem = syscall_write_mem;
cb_syscall (cb, &s);
fr30bf_h_gr_set (current_cpu, 2, s.errcode); /* TODO: check this one */
fr30bf_h_gr_set (current_cpu, 4, s.result);
fr30bf_h_gr_set (current_cpu, 1, s.result2); /* TODO: check this one */
break;
}
case TRAP_BREAKPOINT:
sim_engine_halt (sd, current_cpu, NULL, pc,
sim_stopped, SIM_SIGTRAP);
break;
default :
{
USI new_pc;
setup_int (current_cpu, pc);
fr30bf_h_ibit_set (current_cpu, 0);
new_pc = GETMEMSI (current_cpu, pc,
fr30bf_h_dr_get (current_cpu, H_DR_TBR)
+ 1024 - ((num + 1) * 4));
return new_pc;
}
}
/* Fake an "reti" insn.
Since we didn't push anything to stack, all we need to do is
update pc. */
return pc + 2;
}
