static unsigned int __init init_chipset_siimage (struct pci_dev *dev, const char *name)
{
u32 class_rev = 0;
u8 tmpbyte = 0;
u8 BA5_EN = 0;
pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
class_rev &= 0xff;
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
pci_read_config_byte(dev, 0x8A, &BA5_EN);
if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
if (setup_mmio_siimage(dev, name)) {
return 0;
}
}
pci_write_config_byte(dev, 0x80, 0x00);
pci_write_config_byte(dev, 0x84, 0x00);
pci_read_config_byte(dev, 0x8A, &tmpbyte);
switch(tmpbyte & 0x30) {
case 0x00:
/* 133 clock attempt to force it on */
pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
case 0x30:
/* if clocking is disabled */
/* 133 clock attempt to force it on */
pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
case 0x10:
/* 133 already */
break;
case 0x20:
/* BIOS set PCI x2 clocking */
break;
}
pci_read_config_byte(dev, 0x8A, &tmpbyte);
pci_write_config_byte(dev, 0xA1, 0x72);
pci_write_config_word(dev, 0xA2, 0x328A);
pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
pci_write_config_dword(dev, 0xA8, 0x43924392);
pci_write_config_dword(dev, 0xAC, 0x40094009);
pci_write_config_byte(dev, 0xB1, 0x72);
pci_write_config_word(dev, 0xB2, 0x328A);
pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
pci_write_config_dword(dev, 0xB8, 0x43924392);
pci_write_config_dword(dev, 0xBC, 0x40094009);
proc_reports_siimage(dev, (tmpbyte>>4), name);
return 0;
}
static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev,
const char *name)
{
unsigned long base, scsc_addr;
void __iomem *ioaddr = NULL;
u8 rev = dev->revision, tmp, BA5_EN;
pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
pci_read_config_byte(dev, 0x8A, &BA5_EN);
if ((BA5_EN & 0x01) || pci_resource_start(dev, 5))
if (setup_mmio_siimage(dev, name))
ioaddr = pci_get_drvdata(dev);
base = (unsigned long)ioaddr;
if (ioaddr && pdev_is_sata(dev)) {
u32 tmp32, irq_mask;
/* make sure IDE0/1 interrupts are not masked */
irq_mask = (1 << 22) | (1 << 23);
tmp32 = readl(ioaddr + 0x48);
if (tmp32 & irq_mask) {
tmp32 &= ~irq_mask;
writel(tmp32, ioaddr + 0x48);
readl(ioaddr + 0x48); /* flush */
}
writel(0, ioaddr + 0x148);
writel(0, ioaddr + 0x1C8);
}
sil_iowrite8(dev, 0, base ? (base + 0xB4) : 0x80);
sil_iowrite8(dev, 0, base ? (base + 0xF4) : 0x84);
scsc_addr = base ? (base + 0x4A) : 0x8A;
tmp = sil_ioread8(dev, scsc_addr);
switch (tmp & 0x30) {
case 0x00:
/* On 100 MHz clocking, try and switch to 133 MHz */
sil_iowrite8(dev, tmp | 0x10, scsc_addr);
break;
case 0x30:
/* Clocking is disabled, attempt to force 133MHz clocking. */
sil_iowrite8(dev, tmp & ~0x20, scsc_addr);
case 0x10:
/* On 133Mhz clocking. */
break;
case 0x20:
/* On PCIx2 clocking. */
break;
}
tmp = sil_ioread8(dev, scsc_addr);
sil_iowrite8 (dev, 0x72, base + 0xA1);
sil_iowrite16(dev, 0x328A, base + 0xA2);
sil_iowrite32(dev, 0x62DD62DD, base + 0xA4);
sil_iowrite32(dev, 0x43924392, base + 0xA8);
sil_iowrite32(dev, 0x40094009, base + 0xAC);
sil_iowrite8 (dev, 0x72, base ? (base + 0xE1) : 0xB1);
sil_iowrite16(dev, 0x328A, base ? (base + 0xE2) : 0xB2);
sil_iowrite32(dev, 0x62DD62DD, base ? (base + 0xE4) : 0xB4);
sil_iowrite32(dev, 0x43924392, base ? (base + 0xE8) : 0xB8);
sil_iowrite32(dev, 0x40094009, base ? (base + 0xEC) : 0xBC);
if (base && pdev_is_sata(dev)) {
writel(0xFFFF0000, ioaddr + 0x108);
writel(0xFFFF0000, ioaddr + 0x188);
writel(0x00680000, ioaddr + 0x148);
writel(0x00680000, ioaddr + 0x1C8);
}
/* report the clocking mode of the controller */
if (!pdev_is_sata(dev)) {
static const char *clk_str[] =
{ "== 100", "== 133", "== 2X PCI", "DISABLED!" };
tmp >>= 4;
printk(KERN_INFO "%s: BASE CLOCK %s\n", name, clk_str[tmp & 3]);
}
return 0;
}
