void setup_usb_host2(void)
{
printk(BIOS_INFO, "Setting up USB HOST2 controller...\n");
setbits_le32(tcsr_usb_sel, 1 << 1); /* Select DWC3 controller */
setup_phy(usb_host2_phy);
setup_dwc3(usb_host2_dwc3);
tune_phy(usb_host2_phy);
}
static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
to_mdp4_lcdc_encoder(encoder);
unsigned long pc = mdp4_lcdc_encoder->pixclock;
struct mdp4_kms *mdp4_kms = get_kms(encoder);
struct drm_panel *panel;
uint32_t config;
int i, ret;
if (WARN_ON(mdp4_lcdc_encoder->enabled))
return;
/* TODO: hard-coded for 18bpp: */
config =
MDP4_DMA_CONFIG_R_BPC(BPC6) |
MDP4_DMA_CONFIG_G_BPC(BPC6) |
MDP4_DMA_CONFIG_B_BPC(BPC6) |
MDP4_DMA_CONFIG_PACK(0x21) |
MDP4_DMA_CONFIG_DEFLKR_EN |
MDP4_DMA_CONFIG_DITHER_EN;
if (!of_property_read_bool(dev->dev->of_node, "qcom,lcdc-align-lsb"))
config |= MDP4_DMA_CONFIG_PACK_ALIGN_MSB;
mdp4_crtc_set_config(encoder->crtc, config);
mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 0);
bs_set(mdp4_lcdc_encoder, 1);
for (i = 0; i < ARRAY_SIZE(mdp4_lcdc_encoder->regs); i++) {
ret = regulator_enable(mdp4_lcdc_encoder->regs[i]);
if (ret)
DRM_DEV_ERROR(dev->dev, "failed to enable regulator: %d\n", ret);
}
DBG("setting lcdc_clk=%lu", pc);
ret = clk_set_rate(mdp4_lcdc_encoder->lcdc_clk, pc);
if (ret)
DRM_DEV_ERROR(dev->dev, "failed to configure lcdc_clk: %d\n", ret);
ret = clk_prepare_enable(mdp4_lcdc_encoder->lcdc_clk);
if (ret)
DRM_DEV_ERROR(dev->dev, "failed to enable lcdc_clk: %d\n", ret);
panel = of_drm_find_panel(mdp4_lcdc_encoder->panel_node);
if (!IS_ERR(panel)) {
drm_panel_prepare(panel);
drm_panel_enable(panel);
}
setup_phy(encoder);
mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 1);
mdp4_lcdc_encoder->enabled = true;
}
static int emaclite_start(struct udevice *dev)
{
struct xemaclite *emaclite = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_platdata(dev);
struct emaclite_regs *regs = emaclite->regs;
debug("EmacLite Initialization Started\n");
/*
* TX - TX_PING & TX_PONG initialization
*/
/* Restart PING TX */
__raw_writel(0, ®s->tx_ping_tsr);
/* Copy MAC address */
xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping,
ENET_ADDR_LENGTH);
/* Set the length */
__raw_writel(ENET_ADDR_LENGTH, ®s->tx_ping_tplr);
/* Update the MAC address in the EMAC Lite */
__raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_ping_tsr);
/* Wait for EMAC Lite to finish with the MAC address update */
while ((__raw_readl(®s->tx_ping_tsr) &
XEL_TSR_PROG_MAC_ADDR) != 0)
;
if (emaclite->txpp) {
/* The same operation with PONG TX */
__raw_writel(0, ®s->tx_pong_tsr);
xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong,
ENET_ADDR_LENGTH);
__raw_writel(ENET_ADDR_LENGTH, ®s->tx_pong_tplr);
__raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_pong_tsr);
while ((__raw_readl(®s->tx_pong_tsr) &
XEL_TSR_PROG_MAC_ADDR) != 0)
;
}
/*
* RX - RX_PING & RX_PONG initialization
*/
/* Write out the value to flush the RX buffer */
__raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_ping_rsr);
if (emaclite->rxpp)
__raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_pong_rsr);
__raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, ®s->mdioctrl);
if (__raw_readl(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
if (!setup_phy(dev))
return -1;
debug("EmacLite Initialization complete\n");
return 0;
}
static void mdp4_lcdc_encoder_enable(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct mdp4_lcdc_encoder *mdp4_lcdc_encoder =
to_mdp4_lcdc_encoder(encoder);
unsigned long pc = mdp4_lcdc_encoder->pixclock;
struct mdp4_kms *mdp4_kms = get_kms(encoder);
struct drm_panel *panel = mdp4_lcdc_encoder->panel;
int i, ret;
if (WARN_ON(mdp4_lcdc_encoder->enabled))
return;
/* TODO: hard-coded for 18bpp: */
mdp4_crtc_set_config(encoder->crtc,
MDP4_DMA_CONFIG_R_BPC(BPC6) |
MDP4_DMA_CONFIG_G_BPC(BPC6) |
MDP4_DMA_CONFIG_B_BPC(BPC6) |
MDP4_DMA_CONFIG_PACK_ALIGN_MSB |
MDP4_DMA_CONFIG_PACK(0x21) |
MDP4_DMA_CONFIG_DEFLKR_EN |
MDP4_DMA_CONFIG_DITHER_EN);
mdp4_crtc_set_intf(encoder->crtc, INTF_LCDC_DTV, 0);
bs_set(mdp4_lcdc_encoder, 1);
for (i = 0; i < ARRAY_SIZE(mdp4_lcdc_encoder->regs); i++) {
ret = regulator_enable(mdp4_lcdc_encoder->regs[i]);
if (ret)
dev_err(dev->dev, "failed to enable regulator: %d\n", ret);
}
DBG("setting lcdc_clk=%lu", pc);
ret = clk_set_rate(mdp4_lcdc_encoder->lcdc_clk, pc);
if (ret)
dev_err(dev->dev, "failed to configure lcdc_clk: %d\n", ret);
ret = clk_prepare_enable(mdp4_lcdc_encoder->lcdc_clk);
if (ret)
dev_err(dev->dev, "failed to enable lcdc_clk: %d\n", ret);
if (panel) {
drm_panel_prepare(panel);
drm_panel_enable(panel);
}
setup_phy(encoder);
mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 1);
mdp4_lcdc_encoder->enabled = true;
}
int main (int argc, char* argv[], char* envp[])
{
INT8U error_code;
setup_phy();
/* Clear the RTOS timer */
OSTimeSet(0);
/* SSSInitialTask will initialize the NicheStack
* TCP/IP Stack and then initialize the rest of the Simple Socket Server example
* RTOS structures and tasks.
*/
error_code = OSTaskCreateExt(SSSInitialTask,
NULL,
(void *)&SSSInitialTaskStk[TASK_STACKSIZE],
SSS_INITIAL_TASK_PRIORITY,
SSS_INITIAL_TASK_PRIORITY,
SSSInitialTaskStk,
TASK_STACKSIZE,
NULL,
0);
alt_uCOSIIErrorHandler(error_code, 0);
/*
* As with all MicroC/OS-II designs, once the initial thread(s) and
* associated RTOS resources are declared, we start the RTOS. That's it!
*/
OSStart();
while(1); /* Correct Program Flow never gets here. */
return -1;
}
static int axiemac_init(struct eth_device *dev, bd_t * bis)
{
struct axidma_priv *priv = dev->priv;
struct axi_regs *regs = (struct axi_regs *)dev->iobase;
u32 temp;
debug("axiemac: Init started\n");
/*
* Initialize AXIDMA engine. AXIDMA engine must be initialized before
* AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
* reset, and since AXIDMA reset line is connected to AxiEthernet, this
* would ensure a reset of AxiEthernet.
*/
axi_dma_init(dev);
/* Initialize AxiEthernet hardware. */
if (axi_ethernet_init(dev))
return -1;
/* Disable all RX interrupts before RxBD space setup */
temp = in_be32(&priv->dmarx->control);
temp &= ~XAXIDMA_IRQ_ALL_MASK;
out_be32(&priv->dmarx->control, temp);
/* Start DMA RX channel. Now it's ready to receive data.*/
out_be32(&priv->dmarx->current, (u32)&rx_bd);
/* Setup the BD. */
memset(&rx_bd, 0, sizeof(rx_bd));
rx_bd.next = (u32)&rx_bd;
rx_bd.phys = (u32)&rxframe;
rx_bd.cntrl = sizeof(rxframe);
/* Flush the last BD so DMA core could see the updates */
flush_cache((u32)&rx_bd, sizeof(rx_bd));
/* It is necessary to flush rxframe because if you don't do it
* then cache can contain uninitialized data */
flush_cache((u32)&rxframe, sizeof(rxframe));
/* Start the hardware */
temp = in_be32(&priv->dmarx->control);
temp |= XAXIDMA_CR_RUNSTOP_MASK;
out_be32(&priv->dmarx->control, temp);
/* Rx BD is ready - start */
out_be32(&priv->dmarx->tail, (u32)&rx_bd);
/* Enable TX */
out_be32(®s->tc, XAE_TC_TX_MASK);
/* Enable RX */
out_be32(®s->rcw1, XAE_RCW1_RX_MASK);
/* PHY setup */
if (!setup_phy(dev)) {
axiemac_halt(dev);
return -1;
}
debug("axiemac: Init complete\n");
return 0;
}