void
simulator_command (char *args, int from_tty)
{
if (gdbsim_desc == NULL)
{
/* PREVIOUSLY: The user may give a command before the simulator
is opened. [...] (??? assuming of course one wishes to
continue to allow commands to be sent to unopened simulators,
which isn't entirely unreasonable). */
/* The simulator is a builtin abstraction of a remote target.
Consistent with that model, access to the simulator, via sim
commands, is restricted to the period when the channel to the
simulator is open. */
error ("Not connected to the simulator target");
}
sim_do_command (gdbsim_desc, args);
/* Invalidate the register cache, in case the simulator command does
something funny. */
registers_changed ();
}
static SIM_RC
standard_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt,
char *arg, int is_command)
{
int i,n;
switch ((STANDARD_OPTIONS) opt)
{
case OPTION_VERBOSE:
STATE_VERBOSE_P (sd) = 1;
break;
#ifdef SIM_HAVE_BIENDIAN
case OPTION_ENDIAN:
if (strcmp (arg, "big") == 0)
{
if (WITH_TARGET_BYTE_ORDER == LITTLE_ENDIAN)
{
sim_io_eprintf (sd, "Simulator compiled for little endian only.\n");
return SIM_RC_FAIL;
}
/* FIXME:wip: Need to set something in STATE_CONFIG. */
current_target_byte_order = BIG_ENDIAN;
}
else if (strcmp (arg, "little") == 0)
{
if (WITH_TARGET_BYTE_ORDER == BIG_ENDIAN)
{
sim_io_eprintf (sd, "Simulator compiled for big endian only.\n");
return SIM_RC_FAIL;
}
/* FIXME:wip: Need to set something in STATE_CONFIG. */
current_target_byte_order = LITTLE_ENDIAN;
}
else
{
sim_io_eprintf (sd, "Invalid endian specification `%s'\n", arg);
return SIM_RC_FAIL;
}
break;
#endif
case OPTION_ENVIRONMENT:
if (strcmp (arg, "user") == 0)
STATE_ENVIRONMENT (sd) = USER_ENVIRONMENT;
else if (strcmp (arg, "virtual") == 0)
STATE_ENVIRONMENT (sd) = VIRTUAL_ENVIRONMENT;
else if (strcmp (arg, "operating") == 0)
STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
else
{
sim_io_eprintf (sd, "Invalid environment specification `%s'\n", arg);
return SIM_RC_FAIL;
}
if (WITH_ENVIRONMENT != ALL_ENVIRONMENT
&& WITH_ENVIRONMENT != STATE_ENVIRONMENT (sd))
{
char *type;
switch (WITH_ENVIRONMENT)
{
case USER_ENVIRONMENT: type = "user"; break;
case VIRTUAL_ENVIRONMENT: type = "virtual"; break;
case OPERATING_ENVIRONMENT: type = "operating"; break;
}
sim_io_eprintf (sd, "Simulator compiled for the %s environment only.\n",
type);
return SIM_RC_FAIL;
}
break;
case OPTION_ALIGNMENT:
if (strcmp (arg, "strict") == 0)
{
if (WITH_ALIGNMENT == 0 || WITH_ALIGNMENT == STRICT_ALIGNMENT)
{
current_alignment = STRICT_ALIGNMENT;
break;
}
}
else if (strcmp (arg, "nonstrict") == 0)
{
if (WITH_ALIGNMENT == 0 || WITH_ALIGNMENT == NONSTRICT_ALIGNMENT)
{
current_alignment = NONSTRICT_ALIGNMENT;
break;
}
}
else if (strcmp (arg, "forced") == 0)
{
if (WITH_ALIGNMENT == 0 || WITH_ALIGNMENT == FORCED_ALIGNMENT)
{
current_alignment = FORCED_ALIGNMENT;
break;
}
}
else
{
sim_io_eprintf (sd, "Invalid alignment specification `%s'\n", arg);
return SIM_RC_FAIL;
}
switch (WITH_ALIGNMENT)
{
case STRICT_ALIGNMENT:
sim_io_eprintf (sd, "Simulator compiled for strict alignment only.\n");
break;
case NONSTRICT_ALIGNMENT:
sim_io_eprintf (sd, "Simulator compiled for nonstrict alignment only.\n");
break;
case FORCED_ALIGNMENT:
sim_io_eprintf (sd, "Simulator compiled for forced alignment only.\n");
break;
}
return SIM_RC_FAIL;
case OPTION_DEBUG:
if (! WITH_DEBUG)
sim_io_eprintf (sd, "Debugging not compiled in, `-D' ignored\n");
else
{
for (n = 0; n < MAX_NR_PROCESSORS; ++n)
for (i = 0; i < MAX_DEBUG_VALUES; ++i)
CPU_DEBUG_FLAGS (STATE_CPU (sd, n))[i] = 1;
}
break;
case OPTION_DEBUG_INSN :
if (! WITH_DEBUG)
sim_io_eprintf (sd, "Debugging not compiled in, `--debug-insn' ignored\n");
else
{
for (n = 0; n < MAX_NR_PROCESSORS; ++n)
CPU_DEBUG_FLAGS (STATE_CPU (sd, n))[DEBUG_INSN_IDX] = 1;
}
break;
case OPTION_DEBUG_FILE :
if (! WITH_DEBUG)
sim_io_eprintf (sd, "Debugging not compiled in, `--debug-file' ignored\n");
else
{
FILE *f = fopen (arg, "w");
if (f == NULL)
{
sim_io_eprintf (sd, "Unable to open debug output file `%s'\n", arg);
return SIM_RC_FAIL;
}
for (n = 0; n < MAX_NR_PROCESSORS; ++n)
CPU_DEBUG_FILE (STATE_CPU (sd, n)) = f;
}
break;
#ifdef SIM_H8300 /* FIXME: Can be moved to h8300 dir. */
case OPTION_H8300:
set_h8300h (1,0);
break;
case OPTION_H8300S:
set_h8300h (1,1);
break;
#endif
#ifdef SIM_HAVE_FLATMEM
case OPTION_MEM_SIZE:
{
unsigned long ul = strtol (arg, NULL, 0);
/* 16384: some minimal amount */
if (! isdigit (arg[0]) || ul < 16384)
{
sim_io_eprintf (sd, "Invalid memory size `%s'", arg);
return SIM_RC_FAIL;
}
STATE_MEM_SIZE (sd) = ul;
}
break;
#endif
case OPTION_DO_COMMAND:
sim_do_command (sd, arg);
break;
case OPTION_ARCHITECTURE:
{
const struct bfd_arch_info *ap = bfd_scan_arch (arg);
if (ap == NULL)
{
sim_io_eprintf (sd, "Architecture `%s' unknown\n", arg);
return SIM_RC_FAIL;
}
STATE_ARCHITECTURE (sd) = ap;
break;
}
case OPTION_ARCHITECTURE_INFO:
{
const char **list = bfd_arch_list();
const char **lp;
if (list == NULL)
abort ();
sim_io_printf (sd, "Possible architectures:");
for (lp = list; *lp != NULL; lp++)
sim_io_printf (sd, " %s", *lp);
sim_io_printf (sd, "\n");
free (list);
break;
}
case OPTION_TARGET:
{
STATE_TARGET (sd) = xstrdup (arg);
break;
}
case OPTION_LOAD_LMA:
{
STATE_LOAD_AT_LMA_P (sd) = 1;
break;
}
case OPTION_LOAD_VMA:
{
STATE_LOAD_AT_LMA_P (sd) = 0;
break;
}
case OPTION_HELP:
sim_print_help (sd, is_command);
if (STATE_OPEN_KIND (sd) == SIM_OPEN_STANDALONE)
exit (0);
/* FIXME: 'twould be nice to do something similar if gdb. */
break;
}
return SIM_RC_OK;
}
SIM_DESC
sim_open (SIM_OPEN_KIND kind,
host_callback *cb,
struct bfd *abfd,
char **argv)
{
int i;
SIM_DESC sd = sim_state_alloc (kind, cb);
mn10300_callback = cb;
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
/* The cpu data is kept in a separately allocated chunk of memory. */
if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
return 0;
/* for compatibility */
simulator = sd;
/* FIXME: should be better way of setting up interrupts. For
moment, only support watchpoints causing a breakpoint (gdb
halt). */
STATE_WATCHPOINTS (sd)->pc = &(PC);
STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
STATE_WATCHPOINTS (sd)->interrupt_handler = NULL;
STATE_WATCHPOINTS (sd)->interrupt_names = NULL;
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
return 0;
sim_add_option_table (sd, NULL, mn10300_options);
/* Allocate core managed memory */
sim_do_command (sd, "memory region 0,0x100000");
sim_do_command (sd, "memory region 0x40000000,0x200000");
/* getopt will print the error message so we just have to exit if this fails.
FIXME: Hmmm... in the case of gdb we need getopt to call
print_filtered. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
if ( NULL != board
&& (strcmp(board, BOARD_AM32) == 0 ) )
{
/* environment */
STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
sim_do_command (sd, "memory region 0x44000000,0x40000");
sim_do_command (sd, "memory region 0x48000000,0x400000");
/* device support for mn1030002 */
/* interrupt controller */
sim_hw_parse (sd, "/mn103int@0x34000100/reg 0x34000100 0x7C 0x34000200 0x8 0x34000280 0x8");
/* DEBUG: NMI input's */
sim_hw_parse (sd, "/glue@0x30000000/reg 0x30000000 12");
sim_hw_parse (sd, "/glue@0x30000000 > int0 nmirq /mn103int");
sim_hw_parse (sd, "/glue@0x30000000 > int1 watchdog /mn103int");
sim_hw_parse (sd, "/glue@0x30000000 > int2 syserr /mn103int");
/* DEBUG: ACK input */
sim_hw_parse (sd, "/glue@0x30002000/reg 0x30002000 4");
sim_hw_parse (sd, "/glue@0x30002000 > int ack /mn103int");
/* DEBUG: LEVEL output */
sim_hw_parse (sd, "/glue@0x30004000/reg 0x30004000 8");
sim_hw_parse (sd, "/mn103int > nmi int0 /glue@0x30004000");
sim_hw_parse (sd, "/mn103int > level int1 /glue@0x30004000");
/* DEBUG: A bunch of interrupt inputs */
sim_hw_parse (sd, "/glue@0x30006000/reg 0x30006000 32");
sim_hw_parse (sd, "/glue@0x30006000 > int0 irq-0 /mn103int");
sim_hw_parse (sd, "/glue@0x30006000 > int1 irq-1 /mn103int");
sim_hw_parse (sd, "/glue@0x30006000 > int2 irq-2 /mn103int");
sim_hw_parse (sd, "/glue@0x30006000 > int3 irq-3 /mn103int");
sim_hw_parse (sd, "/glue@0x30006000 > int4 irq-4 /mn103int");
sim_hw_parse (sd, "/glue@0x30006000 > int5 irq-5 /mn103int");
sim_hw_parse (sd, "/glue@0x30006000 > int6 irq-6 /mn103int");
sim_hw_parse (sd, "/glue@0x30006000 > int7 irq-7 /mn103int");
/* processor interrupt device */
/* the device */
sim_hw_parse (sd, "/mn103cpu@0x20000000");
sim_hw_parse (sd, "/mn103cpu@0x20000000/reg 0x20000000 0x42");
/* DEBUG: ACK output wired upto a glue device */
sim_hw_parse (sd, "/glue@0x20002000");
sim_hw_parse (sd, "/glue@0x20002000/reg 0x20002000 4");
sim_hw_parse (sd, "/mn103cpu > ack int0 /glue@0x20002000");
/* DEBUG: RESET/NMI/LEVEL wired up to a glue device */
sim_hw_parse (sd, "/glue@0x20004000");
sim_hw_parse (sd, "/glue@0x20004000/reg 0x20004000 12");
sim_hw_parse (sd, "/glue@0x20004000 > int0 reset /mn103cpu");
sim_hw_parse (sd, "/glue@0x20004000 > int1 nmi /mn103cpu");
sim_hw_parse (sd, "/glue@0x20004000 > int2 level /mn103cpu");
/* REAL: The processor wired up to the real interrupt controller */
sim_hw_parse (sd, "/mn103cpu > ack ack /mn103int");
sim_hw_parse (sd, "/mn103int > level level /mn103cpu");
sim_hw_parse (sd, "/mn103int > nmi nmi /mn103cpu");
/* PAL */
/* the device */
sim_hw_parse (sd, "/pal@0x31000000");
sim_hw_parse (sd, "/pal@0x31000000/reg 0x31000000 64");
sim_hw_parse (sd, "/pal@0x31000000/poll? true");
/* DEBUG: PAL wired up to a glue device */
sim_hw_parse (sd, "/glue@0x31002000");
sim_hw_parse (sd, "/glue@0x31002000/reg 0x31002000 16");
sim_hw_parse (sd, "/pal@0x31000000 > countdown int0 /glue@0x31002000");
sim_hw_parse (sd, "/pal@0x31000000 > timer int1 /glue@0x31002000");
sim_hw_parse (sd, "/pal@0x31000000 > int int2 /glue@0x31002000");
sim_hw_parse (sd, "/glue@0x31002000 > int0 int3 /glue@0x31002000");
sim_hw_parse (sd, "/glue@0x31002000 > int1 int3 /glue@0x31002000");
sim_hw_parse (sd, "/glue@0x31002000 > int2 int3 /glue@0x31002000");
/* REAL: The PAL wired up to the real interrupt controller */
sim_hw_parse (sd, "/pal@0x31000000 > countdown irq-0 /mn103int");
sim_hw_parse (sd, "/pal@0x31000000 > timer irq-1 /mn103int");
sim_hw_parse (sd, "/pal@0x31000000 > int irq-2 /mn103int");
/* 8 and 16 bit timers */
sim_hw_parse (sd, "/mn103tim@0x34001000/reg 0x34001000 36 0x34001080 100 0x34004000 16");
/* Hook timer interrupts up to interrupt controller */
sim_hw_parse (sd, "/mn103tim > timer-0-underflow timer-0-underflow /mn103int");
sim_hw_parse (sd, "/mn103tim > timer-1-underflow timer-1-underflow /mn103int");
sim_hw_parse (sd, "/mn103tim > timer-2-underflow timer-2-underflow /mn103int");
sim_hw_parse (sd, "/mn103tim > timer-3-underflow timer-3-underflow /mn103int");
sim_hw_parse (sd, "/mn103tim > timer-4-underflow timer-4-underflow /mn103int");
sim_hw_parse (sd, "/mn103tim > timer-5-underflow timer-5-underflow /mn103int");
sim_hw_parse (sd, "/mn103tim > timer-6-underflow timer-6-underflow /mn103int");
sim_hw_parse (sd, "/mn103tim > timer-6-compare-a timer-6-compare-a /mn103int");
sim_hw_parse (sd, "/mn103tim > timer-6-compare-b timer-6-compare-b /mn103int");
/* Serial devices 0,1,2 */
sim_hw_parse (sd, "/mn103ser@0x34000800/reg 0x34000800 48");
sim_hw_parse (sd, "/mn103ser@0x34000800/poll? true");
/* Hook serial interrupts up to interrupt controller */
sim_hw_parse (sd, "/mn103ser > serial-0-receive serial-0-receive /mn103int");
sim_hw_parse (sd, "/mn103ser > serial-0-transmit serial-0-transmit /mn103int");
sim_hw_parse (sd, "/mn103ser > serial-1-receive serial-1-receive /mn103int");
sim_hw_parse (sd, "/mn103ser > serial-1-transmit serial-1-transmit /mn103int");
sim_hw_parse (sd, "/mn103ser > serial-2-receive serial-2-receive /mn103int");
sim_hw_parse (sd, "/mn103ser > serial-2-transmit serial-2-transmit /mn103int");
sim_hw_parse (sd, "/mn103iop@0x36008000/reg 0x36008000 8 0x36008020 8 0x36008040 0xc 0x36008060 8 0x36008080 8");
/* Memory control registers */
sim_do_command (sd, "memory region 0x32000020,0x30");
/* Cache control register */
sim_do_command (sd, "memory region 0x20000070,0x4");
/* Cache purge regions */
sim_do_command (sd, "memory region 0x28400000,0x800");
sim_do_command (sd, "memory region 0x28401000,0x800");
/* DMA registers */
sim_do_command (sd, "memory region 0x32000100,0xF");
sim_do_command (sd, "memory region 0x32000200,0xF");
sim_do_command (sd, "memory region 0x32000400,0xF");
sim_do_command (sd, "memory region 0x32000800,0xF");
}
else
{
if (board != NULL)
{
sim_io_eprintf (sd, "Error: Board `%s' unknown.\n", board);
return 0;
}
}
/* check for/establish the a reference program image */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
? *STATE_PROG_ARGV (sd)
: NULL),
abfd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
/* establish any remaining configuration options */
if (sim_config (sd) != SIM_RC_OK)
{
sim_module_uninstall (sd);
return 0;
}
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
file descriptor leaks, etc. */
sim_module_uninstall (sd);
return 0;
}
/* set machine specific configuration */
/* STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */
/* | PSW_CY | PSW_OV | PSW_S | PSW_Z); */
/* CPU specific initialization. */
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *cpu = STATE_CPU (sd, i);
CPU_PC_FETCH (cpu) = mn10300_pc_get;
CPU_PC_STORE (cpu) = mn10300_pc_set;
}
return sd;
}
