SF
sh64_fnegs(SIM_CPU *current_cpu, SF frgh)
{
SF result;
sim_fpu f, fres;
sim_fpu_32to (&f, frgh);
sim_fpu_neg (&fres, &f);
sim_fpu_to32 (&result, &fres);
return result;
}
DF
sh64_fnegd(SIM_CPU *current_cpu, DF drgh)
{
DF result;
sim_fpu f1, f2;
sim_fpu_64to (&f1, drgh);
sim_fpu_neg (&f2, &f1);
sim_fpu_to64 (&result, &f2);
return result;
}
static SF
negsf (CGEN_FPU* fpu, SF x)
{
sim_fpu op1;
sim_fpu ans;
unsigned32 res;
sim_fpu_status status;
sim_fpu_32to (&op1, x);
status = sim_fpu_neg (&ans, &op1);
if (status != 0)
(*fpu->ops->error) (fpu, status);
sim_fpu_to32 (&res, &ans);
return res;
}
static DF
negdf (CGEN_FPU* fpu, DF x)
{
sim_fpu op1;
sim_fpu ans;
unsigned64 res;
sim_fpu_status status;
sim_fpu_64to (&op1, x);
status = sim_fpu_neg (&ans, &op1);
if (status != 0)
(*fpu->ops->error) (fpu, status);
sim_fpu_to64 (&res, &ans);
return res;
}
/* Implement a 32/64 bit FP nmadd, setting FP exception bits when
appropriate. */
void
fpu_fnmadd (SIM_DESC sd, sim_cpu *cpu, sim_cia cia,
const void *reg_in1, const void *reg_in2, const void *reg_in3,
void *reg_out, const struct fp_prec_t *ops)
{
sim_fpu m1, m2, m, mm, n, r;
REG2VAL (reg_in1, &m1);
REG2VAL (reg_in2, &m2);
REG2VAL (reg_in3, &n);
ROUND (&m1);
ROUND (&m2);
ROUND (&n);
FPCR &= ~ EC_MASK;
if (sim_fpu_is_snan (&m1) || sim_fpu_is_snan (&m2) || sim_fpu_is_snan (&n)
|| (sim_fpu_is_infinity (&m1) && sim_fpu_is_zero (&m2))
|| (sim_fpu_is_zero (&m1) && sim_fpu_is_infinity (&m2)))
{
invalid_operands:
if (FPCR & EE_V)
FPCR |= EC_V;
else
VAL2REG (&sim_fpu_qnan, reg_out);
}
else
{
sim_fpu_status stat = sim_fpu_mul (&m, &m1, &m2);
if (sim_fpu_is_infinity (&m) && sim_fpu_is_infinity (&n)
&& sim_fpu_sign (&m) == sim_fpu_sign (&n))
goto invalid_operands;
stat |= sim_fpu_neg (&mm, &m);
stat |= sim_fpu_add (&r, &mm, &n);
stat |= ROUND (&r);
if (fpu_status_ok (stat))
VAL2REG (&r, reg_out);
}
fpu_check_signal_exception (sd, cpu, cia);
}
