/* Walks back from n until it finds a real cf op. */
static ir_node *get_cf_op(ir_node *n)
{
while (!is_cfop(n) && !is_fragile_op(n) && !is_Bad(n)) {
n = skip_Tuple(n);
n = skip_Proj(n);
}
return n;
}
/**
* Transforms a Div into the appropriate soft float function.
*/
static bool lower_Div(ir_node *const n)
{
ir_mode *const mode = get_Div_resmode(n);
if (!mode_is_float(mode))
return false;
ir_node *const left = get_Div_left(n);
ir_node *const right = get_Div_right(n);
ir_node *const in[] = { left, right };
ir_node *const result = make_softfloat_call(n, "div", ARRAY_SIZE(in), in);
ir_node *const call = skip_Proj(skip_Proj(result));
set_irn_pinned(call, get_irn_pinned(n));
foreach_out_edge_safe(n, edge) {
ir_node *proj = get_edge_src_irn(edge);
if (!is_Proj(proj))
continue;
switch ((pn_Div)get_Proj_num(proj)) {
case pn_Div_M:
set_Proj_pred(proj, call);
set_Proj_num(proj, pn_Call_M);
continue;
case pn_Div_X_regular:
set_Proj_pred(proj, call);
set_Proj_num(proj, pn_Call_X_regular);
continue;
case pn_Div_X_except:
set_Proj_pred(proj, call);
set_Proj_num(proj, pn_Call_X_except);
continue;
case pn_Div_res:
exchange(proj, result);
continue;
}
panic("unexpected Proj number");
}
static ir_node *create_fpu_mode_spill(void *const env, ir_node *const state, bool const force, ir_node *const after)
{
(void)env;
if (!force && is_ia32_ChangeCW(state))
return NULL;
ir_node *spill;
ir_node *const block = get_nodes_block(state);
/* Don't spill the fpcw in unsafe mode. */
if (ia32_cg_config.use_unsafe_floatconv) {
spill = new_bd_ia32_FnstCWNOP(NULL, block, state);
} else {
ir_graph *const irg = get_irn_irg(state);
ir_node *const noreg = ia32_new_NoReg_gp(irg);
ir_node *const nomem = get_irg_no_mem(irg);
ir_node *const frame = get_irg_frame(irg);
spill = create_fnstcw(block, frame, noreg, nomem, state);
}
sched_add_after(skip_Proj(after), spill);
return spill;
}
