void
lpc2210_uart_write(ARMul_State *state, ARMword addr, ARMword data,int i)
{
static ARMword tx_buf = 0;
//DBG_PRINT("uart_write(0x%x, 0x%x)\n", (addr & 0xfff) >> 2, data);
switch ((addr & 0xfff) >> 2) {
case 0x0: // THR
{
char c = data;
/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
skyeye_uart_write(-1, &c, 1, NULL);
//io.uart[0].lsr |= 0x40;
io.uart[0].lsr |= 0x20;
}
case 0x2: //FCR
{
io.uart[i].fcr = data;
break;
}
case 0x7: // SCR
io.uart[i].scr = data;
break;
default:
//printf("%c", data); fflush(stdout);
DBG_PRINT("uart_write(%s=0x%08x)\n", "uart_reg", addr);
break;
}
}
static void
ep9312_uart_write (ARMul_State * state, u32 offset, u32 data, int index)
{
switch (offset) {
case UART_DR:
{
char c = data;
/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
skyeye_uart_write(-1, &c, 1, NULL);
}
case UART_RSR:
//case UART_ECR:
case UART_CR_H:
case UART_CR_M:
case UART_CR_L:
break;
case UART_CR:
{
io.uart[index].cr = data;
if ((data & AMBA_UARTCR_TIE) == 0) {
io.intmr[0] &= ~(UART_TXINTR[index]);
io.intsr[0] &= ~(UART_TXINTR[index]);
io.intsr[1] &= ~(INT_UART[index]);
io.intmr[1] &= ~(INT_UART[index]);
io.uart[index].iir &= ~(UART_IIR_TIS); //Interrupt Identification and Clear
}
else {
io.intmr[0] |= (UART_TXINTR[index]);
io.intsr[0] |= (UART_TXINTR[index]);
io.intsr[1] = (INT_UART[index]);
io.intmr[1] = (INT_UART[index]);
io.uart[index].iir |= (UART_IIR_TIS);
}
extern ARMul_State * state;
ep9312_update_int (state);
}
break;
case UART_FR:
case UART_IIR:
io.uart[index].iir = data;
break;
//case UART_ICR:
case UART_ILPR:
case UART_DMACR:
case UART_TCR:
case UART_TISR:
case UART_TOCR:
case UART_TMR:
case UART_MCR:
case UART_MSR:
break;
default:
SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data);
}
}
static void
s3c2440_uart_write (ARMul_State * mstate, u32 offset, u32 data)
{
SKYEYE_DBG ("s3c2440_uart_write(0x%x, 0x%x)\n", offset, data);
switch (offset) {
case ULCON:
io.uart0.ulcon = data;
break;
case UCON:
io.uart0.ucon = data;
break;
case UFCON:
io.uart0.ufcon = data;
break;
case UMCON:
io.uart0.umcon = data;
break;
case UTRSTAT:
io.uart0.utrstat = data;
break;
case UERSTAT:
io.uart0.uerstat = data;
break;
case UFSTAT:
io.uart0.ufstat = data;
break;
case UMSTAT:
io.uart0.umstat = data;
break;
case UTXH:
{
char c = data;
/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
skyeye_uart_write(-1, &c, 1, NULL);
io.uart0.utrstat |= 0x6; //set strstat register bit[0]
if ((io.uart0.ucon & 0xc) == 0x4) {
s3c2440_set_subsrcint (UART_INT_TXD <<
(0 * 3));
extern ARMul_State *state;
s3c2440_update_int (state);
}
}
break;
case UBRDIV:
io.uart0.ubrdiv = data;
break;
default:
break;
}
SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data);
}
static void
ns9750_uart_write (void *state, u32 offset, u32 data)
{
SKYEYE_DBG ("ns9750_uart_write(0x%x, 0x%x)\n", offset, data);
switch (offset) {
case US_CR:
io.uart0.cr = data;
break;
case US_MR:
io.uart0.mr = data;
break;
case US_IER:
//io.uart0.ier = data;
io.uart0.imr |= (data & 0x000f3fff);
if (io.uart0.imr) {
io.ipr |= AT91RM92_ID_US0;
ns9750_update_int (state);
}
break;
case US_IDR:
/* disable usart0 corresponding interrupt
* */
io.uart0.imr &= (~data) & 0x000f3fff;
break;
case US_THR:
{
char c = data;
/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
skyeye_uart_write(-1, &c, 1, NULL);
io.uart0.csr |= AT91RM92_US_TXRDY;
}
//io.uart0.thr = data;
break;
case US_BRGR:
io.uart0.brgr = data;
break;
case US_RTOR:
io.uart0.rtor = data;
break;
case US_TTGR:
io.uart0.ttgr = data;
break;
case US_FIDI:
io.uart0.fidi = data;
break;
case US_IF:
io.uart0.us_if = data;
break;
}
SKYEYE_DBG ("%s(0x%x, 0x%x)\n", __func__, offset, data);
}
/*
* === FUNCTION ======================================================================
* Name: leon2_uart_cycle
* Description: This function performs the execution of the UART cycle. The
* function checks whether there is some to transmit from the UART.
*
* @TODO: The implementation is not finished. Still the implementation does not
* care about the possible generated interrupts.
* =====================================================================================
*/
void leon2_uart_cycle(void *pstate)
{
/*-----------------------------------------------------------------------------
* TRANSMITER OPERATION
*-----------------------------------------------------------------------------*/
/* Check whether there is something to transmit from the UART. If
* transmitter is enabled through the TE bit in the control register, the
* data is transmiter by means of the skyeye uart */
if( leon2_uart.regs.control.transmitter_enable )
{
if( !leon2_uart.regs.status.transmitter_hold_register_empty )
{
char c = leon2_uart.regs.data;
/* Call the SKYEYE uart function to print out the character */
skyeye_uart_write(-1, &c, 1, NULL);
/* clear the transmitter data register */
// clear_bits(regmap.uart_1_data, LEON2_UART_DATA_last, LEON2_UART_DATA_first);
/* Indicate the transmiter hold register is empty */
leon2_uart.regs.status.transmitter_hold_register_empty = 1;
/* Indicate the transmiter shift register is empty */
leon2_uart.regs.status.transmitter_shift_register_empty = 1;
}
}
else
{
/* UART Transmiter not enabled */
}
/*-----------------------------------------------------------------------------
* RECEIVER OPERATION
*-----------------------------------------------------------------------------*/
}
static exception_t uart_16550_write(conf_object_t *obj, generic_address_t offset, void* buf, size_t count){
uart_16550_t *uart = (uart_16550_t *)(obj->obj);
reg_16550_t* reg = uart->reg;
/* get a reference of object by its name */
switch ((offset & 0xfff) >> 2) {
case 0x0: // THR
{
char c = *(char *)buf;
skyeye_uart_write(-1, &c, 1, NULL);
reg->lsr |= 0x20;
}
case 0x2: //FCR
reg->fcr = *(uint32 *)buf;
break;
case 0x7: // SCR
reg->scr = *(uint32 *)buf;
break;
default:
//DBG_PRINT ("uart_write(%s=0x%08x)\n", "uart_reg", addr);
break;
}
return No_exp;
}
static void
omap5912_io_write_word (void *state, uint32_t addr, uint32_t data)
{
omap_ioreg_t ioregaddr = addr;
#if 1
if ((addr >= UART1_RHR) && (addr <= UART1_WER))
{
switch (addr) {
/**uart 1*/
case UART1_THR:
{
int i;
//omap5912_io.uart.thr = data;
//omap5912_io.uart.dll = data;
unsigned char c = data;
if (skyeye_uart_write(-1, &c, 1, NULL) < 0)
{
return;
}
//omap5912_io.uart.iir = 0x1;
omap5912_io.uart.lsr = 0x60;
//omap5912_io.uart.iir = THR_INT & (0xff);
#if 1
//if transmit interrupt comes
if ((omap5912_io.uart.ier & 0xf) == 0x2)
//if ((omap5912_io.uart.iir & 0xf) == THR_INT)
{
//printf("whyhere\n");
omap5912_io.ic.mpu_l2_itr |= (1<<14);
for (i=31; i>=0; i--)
{
if (omap5912_io.ic.mpu_l2_itr & (1 << i))
break;
}
if (i <=31)
{
omap5912_io.ic.mpu_l2_sir_irq = i;
}
omap5912_update_int(state);
}
#endif
}
//printf("data in thr=%x\n", data);
break;
case UART1_IER:
omap5912_io.uart.ier = data;
// omap5912_io.uart.dlh = data;
// printf("data in ier=%x\n", data);
break;
case UART1_FCR:
omap5912_io.uart.fcr = data;
// omap5912_io.uart.efr = data;
break;
case UART1_LCR:
omap5912_io.uart.lcr = data;
break;
case UART1_MCR:
omap5912_io.uart.mcr = data;
// omap5912_io.uart.xon1 = data;
break;
case UART1_XON2:
omap5912_io.uart.xon2 = data;
break;
case UART1_TCR:
omap5912_io.uart.tcr = data;
//omap5912_io.uart.xoff1 = data;
break;
case UART1_SPR:
omap5912_io.uart.spr = data;
//omap5912_io.uart.tlr = data;
//omap5912_io.uart.xoff2 = data;
break;
case UART1_MDR1:
omap5912_io.uart.mdr1 = data;
break;
case UART1_MDR2:
omap5912_io.uart.mdr2 = data;
break;
case UART1_TXFLL:
omap5912_io.uart.txfll = data;
break;
case UART1_TXFLH:
omap5912_io.uart.txflh = data;
break;
case UART1_RXFLL:
omap5912_io.uart.rxfll = data;
break;
case UART1_SFREGH:
omap5912_io.uart.sfregh = data;
//omap5912_io.uart.rxflh = data;
break;
case UART1_BLR:
omap5912_io.uart.blr = data;
break;
case UART1_ACREG:
omap5912_io.uart.acreg = data;
break;
case UART1_SCR:
omap5912_io.uart.scr = data;
break;
case UART1_SSR:
omap5912_io.uart.ssr = data;
break;
case UART1_EBLR:
omap5912_io.uart.eblr = data;
break;
case UART1_SYSC:
omap5912_io.uart.sysc = data;
break;
case UART1_SYSS:
omap5912_io.uart.syss = data;
break;
case UART1_WER:
omap5912_io.uart.wer = data;
break;
default:
break;
}//?endswitch
}//endif
#endif
if ((ioregaddr >= MPU_L1_ILR0) && (ioregaddr <=MPU_L1_ILR31))
{
int offset = (ioregaddr - MPU_L1_ILR0)/4;
omap5912_io.ic.mpu_l1_ilr[offset] = data;
//printf("mpu l1 ilr[%d] 0x%x\n",offset,data);
return;
}
if ((ioregaddr >= MPU_L2_ILR0) && (ioregaddr <=MPU_L2_ILR31))
{
int offset = (ioregaddr - MPU_L2_ILR0)/4;
omap5912_io.ic.mpu_l2_ilr[offset] = data;
//printf("mpu l2 ilr[%d] 0x%x\n",offset/4,data);
return;
}
if ((ioregaddr >= MPU_L2_ILR0_S1) && (ioregaddr <=MPU_L2_ILR31_S1))
{
int offset = (ioregaddr - MPU_L2_ILR0_S1)/4;
omap5912_io.ic.mpu_l2_ilr_s1[offset] = data;
//printf("mpu l2 ilr[%d] 0x%x\n",offset/4,data);
return;
}
if ((ioregaddr >= MPU_L2_ILR0_S2) && (ioregaddr <=MPU_L2_ILR31_S2))
{
int offset = (ioregaddr - MPU_L2_ILR0_S2)/4;
omap5912_io.ic.mpu_l2_ilr_s2[offset] = data;
//printf("mpu l2 ilr[%d] 0x%x\n",offset/4,data);
return;
}
if ((ioregaddr >= MPU_L2_ILR0_S3) && (ioregaddr <=MPU_L2_ILR31_S3))
{
int offset = (ioregaddr - MPU_L2_ILR0_S3)/4;
omap5912_io.ic.mpu_l2_ilr_s3[offset] = data;
//printf("mpu l2 ilr[%d] 0x%x\n",offset/4,data);
return;
}
switch (ioregaddr) {
/*os timer*/
case OS_TIMER_TICK_VAL:
omap5912_io.os_timer.os_timer_tick_val = data & (0x00ffffff);
break;
case OS_TIMER_CTRL:
omap5912_io.os_timer.os_timer_ctrl = data;
printf("timeros control register %x\n", data);
break;
/*
case TIMER_32K_SYNCHRONIZED:
omap5912_io.timer_32k_synchronized = data;
printf("write 32k synchronized%x\n", data);
break;
*/
/*mpu timer*/
case MPU_CNTL_TIMER1:
omap5912_io.timer.mpu_cntl_timer[0] = data;
break;
case MPU_LOAD_TIMER1:
//omap5912_io.timer.mpu_load_timer[0] = 1000/8/6; //what size should be set?
omap5912_io.timer.mpu_load_timer[0] = data/1000; //what size should be set?
//printf("timer1 load register %x\n", omap5912_io.timer.mpu_load_timer[0]);
break;
case MPU_CNTL_TIMER2:
omap5912_io.timer.mpu_cntl_timer[1] = data;
break;
case MPU_LOAD_TIMER2:
//omap5912_io.timer.mpu_load_timer[1] = (0xffffffff)/(100*1024*1024); //what size should be set?
omap5912_io.timer.mpu_load_timer[1] = data; //what size should be set?
//printf("timer2 load register %x\n", omap5912_io.timer.mpu_load_timer[1]);
break;
case MPU_CNTL_TIMER3:
omap5912_io.timer.mpu_cntl_timer[2] = data;
break;
case MPU_LOAD_TIMER3:
omap5912_io.timer.mpu_load_timer[2] = data;
break;
/**uart 1*/
#if 0
case UART1_THR:
{ omap5912_io.uart.thr = (data & 0xff);
unsigned char c = (data & 0xff);
j = skyeye_uart_write(-1, &c, 1, NULL);
omap5912_io.uart.lsr |= 0x60;
// printf("here,j =%d\n", j);
}
break;
#endif
/** interrupt control*/
case MPU_L2_ITR:
omap5912_io.ic.mpu_l2_itr = data;
//printf("write mpu2_itr data = %x\n", data);
break;
case MPU_L2_MIR:
omap5912_io.ic.mpu_l2_mir = data;
//printf("write mpu2_imr data = %x\n", data);
break;
case MPU_L2_CONTROL:
#if 1
{
int i;
i = omap5912_io.ic.mpu_l2_sir_irq;
//printf("sirirq i = %x\n", i);
omap5912_io.ic.mpu_l2_itr &= ~(1 << i);
}
#endif
omap5912_io.ic.mpu_l2_control = data;
//printf("write mpu2_control data = %x\n", data);
break;
case MPU_L2_ISR:
omap5912_io.ic.mpu_l2_isr = data;
// printf("write mpu2_l2 isr data = %x\n", data);
break;
case MPU_L2_OCP_CFG:
omap5912_io.ic.mpu_l2_ocp_cfg = data;
//printf("write mpu2_l2 ocp cfg data = %x\n", data);
break;
case MPU_L1_ITR:
omap5912_io.ic.mpu_l1_itr = (data &0xffffffff);
//printf("write mpu1_itr data = %x\n", data);
break;
case MPU_L1_MIR:
omap5912_io.ic.mpu_l1_mir = data;
//printf("write mpu1_imr data = %x\n", data);
break;
case MPU_L1_CONTROL:
#if 1
{
int i;
i = omap5912_io.ic.mpu_l1_sir_irq_code;
//printf("sirirq i = %x\n", i);
omap5912_io.ic.mpu_l1_itr &= ~(1 << i);
}
#endif
omap5912_io.ic.mpu_l1_control = data;
//printf("write mpu_l1 control data = %x\n", data);
break;
case MPU_L1_ISR:
omap5912_io.ic.mpu_l1_isr = data;
//printf("write mpu_l1 isr data = %x\n", data);
break;
case MPU_L1_ENHANCEED_CNTL:
omap5912_io.ic.mpu_l1_enhanceed_cntl = data;
//printf("write mpu_l1 enhaced data = %x\n", data);
break;
/** gpio1*/
case GPIO1_SYSCONFIG:
omap5912_io.gpio[0].gpio_sysconfig = data;
break;
case GPIO1_IRQSTATUS1:
omap5912_io.gpio[0].gpio_irqstatus1 = data;
break;
case GPIO1_IRQENABLE1:
omap5912_io.gpio[0].gpio_irqenable1 = data;
break;
case GPIO1_IRQSTATUS2:
omap5912_io.gpio[0].gpio_irqstatus2 = data;
break;
case GPIO1_IRQENABLE2:
omap5912_io.gpio[0].gpio_irqenable2 = data;
break;
case GPIO1_WAKEUPENABLE:
omap5912_io.gpio[0].gpio_wakeupenable = data;
break;
// case GPIO1_DATAIN:
// omap5912_io.gpio[0].gpio_datain = data;
// break;
case GPIO1_DATAOUT:
omap5912_io.gpio[0].gpio_dataout = data;
break;
case GPIO1_DIRECTION:
omap5912_io.gpio[0].gpio_direction = data;
break;
case GPIO1_EDGE_CTRL1:
omap5912_io.gpio[0].gpio_edge_ctrl1 = data;
break;
case GPIO1_EDGE_CTRL2:
omap5912_io.gpio[0].gpio_edge_ctrl2 = data;
break;
case GPIO1_CLEAR_IRQENABLE1:
omap5912_io.gpio[0].gpio_clear_irqenable1 = data;
break;
case GPIO1_CLEAR_IRQENABLE2:
omap5912_io.gpio[0].gpio_clear_irqenable2 = data;
break;
case GPIO1_CLEAR_WAKEUPENA:
omap5912_io.gpio[0].gpio_clear_wakeupena = data;
break;
case GPIO1_CLEAR_DATAOUT:
omap5912_io.gpio[0].gpio_clear_dataout = data;
break;
case GPIO1_SET_IRQENABLE1:
omap5912_io.gpio[0].gpio_set_irqenable1 = data;
break;
case GPIO1_SET_IRQENABLE2:
omap5912_io.gpio[0].gpio_set_irqenable2 = data;
break;
case GPIO1_SET_WAKEUPENA:
omap5912_io.gpio[0].gpio_set_wakeupena = data;
break;
case GPIO1_SET_DATAOUT:
omap5912_io.gpio[0].gpio_set_dataout = data;
break;
/** gpio2*/
case GPIO2_SYSCONFIG:
omap5912_io.gpio[1].gpio_sysconfig = data;
break;
case GPIO2_IRQSTATUS1:
omap5912_io.gpio[1].gpio_irqstatus1 = data;
break;
case GPIO2_IRQENABLE1:
omap5912_io.gpio[1].gpio_irqenable1 = data;
break;
case GPIO2_IRQSTATUS2:
omap5912_io.gpio[1].gpio_irqstatus2 = data;
break;
case GPIO2_IRQENABLE2:
omap5912_io.gpio[1].gpio_irqenable2 = data;
break;
case GPIO2_WAKEUPENABLE:
omap5912_io.gpio[1].gpio_wakeupenable = data;
break;
case GPIO2_DATAOUT:
omap5912_io.gpio[1].gpio_dataout = data;
break;
case GPIO2_DIRECTION:
omap5912_io.gpio[1].gpio_direction = data;
break;
case GPIO2_EDGE_CTRL1:
omap5912_io.gpio[1].gpio_edge_ctrl1 = data;
break;
case GPIO2_EDGE_CTRL2:
omap5912_io.gpio[1].gpio_edge_ctrl2 = data;
break;
case GPIO2_CLEAR_IRQENABLE1:
omap5912_io.gpio[1].gpio_clear_irqenable1 = data;
break;
case GPIO2_CLEAR_IRQENABLE2:
omap5912_io.gpio[1].gpio_clear_irqenable2 = data;
break;
case GPIO2_CLEAR_WAKEUPENA:
omap5912_io.gpio[1].gpio_clear_wakeupena = data;
break;
case GPIO2_CLEAR_DATAOUT:
omap5912_io.gpio[1].gpio_clear_dataout = data;
break;
case GPIO2_SET_IRQENABLE1:
omap5912_io.gpio[1].gpio_set_irqenable1 = data;
break;
case GPIO2_SET_IRQENABLE2:
omap5912_io.gpio[1].gpio_set_irqenable2 = data;
break;
case GPIO2_SET_WAKEUPENA:
omap5912_io.gpio[1].gpio_set_wakeupena = data;
break;
case GPIO2_SET_DATAOUT:
omap5912_io.gpio[1].gpio_set_dataout = data;
break;
/** gpio2*/
case GPIO3_SYSCONFIG:
omap5912_io.gpio[2].gpio_sysconfig = data;
break;
case GPIO3_IRQSTATUS1:
omap5912_io.gpio[2].gpio_irqstatus1 = data;
break;
case GPIO3_IRQENABLE1:
omap5912_io.gpio[2].gpio_irqenable1 = data;
break;
case GPIO3_IRQSTATUS2:
omap5912_io.gpio[2].gpio_irqstatus2 = data;
break;
case GPIO3_IRQENABLE2:
omap5912_io.gpio[2].gpio_irqenable2 = data;
break;
case GPIO3_WAKEUPENABLE:
omap5912_io.gpio[2].gpio_wakeupenable = data;
break;
case GPIO3_DATAOUT:
omap5912_io.gpio[2].gpio_dataout = data;
break;
case GPIO3_DIRECTION:
omap5912_io.gpio[2].gpio_direction = data;
break;
case GPIO3_EDGE_CTRL1:
omap5912_io.gpio[2].gpio_edge_ctrl1 = data;
break;
case GPIO3_EDGE_CTRL2:
omap5912_io.gpio[2].gpio_edge_ctrl2 = data;
break;
case GPIO3_CLEAR_IRQENABLE1:
omap5912_io.gpio[2].gpio_clear_irqenable1 = data;
break;
case GPIO3_CLEAR_IRQENABLE2:
omap5912_io.gpio[2].gpio_clear_irqenable2 = data;
break;
case GPIO3_CLEAR_WAKEUPENA:
omap5912_io.gpio[2].gpio_clear_wakeupena = data;
break;
case GPIO3_CLEAR_DATAOUT:
omap5912_io.gpio[2].gpio_clear_dataout = data;
break;
case GPIO3_SET_IRQENABLE1:
omap5912_io.gpio[2].gpio_set_irqenable1 = data;
break;
case GPIO3_SET_IRQENABLE2:
omap5912_io.gpio[2].gpio_set_irqenable2 = data;
break;
case GPIO3_SET_WAKEUPENA:
omap5912_io.gpio[2].gpio_set_wakeupena = data;
break;
case GPIO3_SET_DATAOUT:
omap5912_io.gpio[2].gpio_set_dataout = data;
break;
/** gpio4*/
case GPIO4_SYSCONFIG:
omap5912_io.gpio[3].gpio_sysconfig = data;
break;
case GPIO4_IRQSTATUS1:
omap5912_io.gpio[3].gpio_irqstatus1 = data;
break;
case GPIO4_IRQENABLE1:
omap5912_io.gpio[3].gpio_irqenable1 = data;
break;
case GPIO4_IRQSTATUS2:
omap5912_io.gpio[3].gpio_irqstatus2 = data;
break;
case GPIO4_IRQENABLE2:
omap5912_io.gpio[3].gpio_irqenable2 = data;
break;
case GPIO4_WAKEUPENABLE:
omap5912_io.gpio[3].gpio_wakeupenable = data;
break;
case GPIO4_DATAOUT:
omap5912_io.gpio[3].gpio_dataout = data;
break;
case GPIO4_DIRECTION:
omap5912_io.gpio[3].gpio_direction = data;
break;
case GPIO4_EDGE_CTRL1:
omap5912_io.gpio[3].gpio_edge_ctrl1 = data;
break;
case GPIO4_EDGE_CTRL2:
omap5912_io.gpio[3].gpio_edge_ctrl2 = data;
break;
case GPIO4_CLEAR_IRQENABLE1:
omap5912_io.gpio[3].gpio_clear_irqenable1 = data;
break;
case GPIO4_CLEAR_IRQENABLE2:
omap5912_io.gpio[3].gpio_clear_irqenable2 = data;
break;
case GPIO4_CLEAR_WAKEUPENA:
omap5912_io.gpio[3].gpio_clear_wakeupena = data;
break;
case GPIO4_CLEAR_DATAOUT:
omap5912_io.gpio[3].gpio_clear_dataout = data;
break;
case GPIO4_SET_IRQENABLE1:
omap5912_io.gpio[3].gpio_set_irqenable1 = data;
break;
case GPIO4_SET_IRQENABLE2:
omap5912_io.gpio[3].gpio_set_irqenable2 = data;
break;
case GPIO4_SET_WAKEUPENA:
omap5912_io.gpio[3].gpio_set_wakeupena = data;
break;
case GPIO4_SET_DATAOUT:
omap5912_io.gpio[3].gpio_set_dataout = data;
break;
case ULPD_CLOCK_CTRL:
omap5912_io.mpu_cfg.ulpd_clock_ctrl = data;
break;
case SOFT_REQ_REG:
omap5912_io.mpu_cfg.soft_req_reg = data;
break;
case SOFT_REQ_REG2:
omap5912_io.mpu_cfg.soft_req_reg2 = data;
break;
case MOD_CONF_CTRL_0:
omap5912_io.mpu_cfg.mod_conf_ctrl_0 = data;
break;
case FUNC_MUX_CTRL_10:
omap5912_io.mpu_cfg.func_mux_ctrl_10 = data;
break;
case PULL_DWN_CTRL_4:
omap5912_io.mpu_cfg.pull_dwn_ctrl_4 = data;
break;
case EMIFS_CS1_CONFIG:
omap5912_io.mpu_cfg.emifs_cs1_config = data;
break;
case ARM_CKCTL:
omap5912_io.mpu_cfg.arm_ckctl = data;
break;
case ARM_IDLECT1:
omap5912_io.mpu_cfg.arm_idlect1 = data;
break;
case ARM_IDLECT2:
omap5912_io.mpu_cfg.arm_idlect2 = data;
break;
case ARM_RSTCT1:
omap5912_io.mpu_cfg.arm_rstct1 = data;
break;
case ARM_RSTCT2:
omap5912_io.mpu_cfg.arm_rstct2 = data;
break;
case ARM_SYSST:
omap5912_io.mpu_cfg.arm_sysst = data;
break;
case DPLL1_CTL_REG:
omap5912_io.mpu_cfg.dpll1_ctl_reg = data;
break;
default:
//SKYEYE_DBG ("io_write_word(0x%08x) = 0x%08x\n", addr, data);
//fprintf(stderr, "ERROR: %s(0x%08x) = 0x%08x\n", __FUNCTION__, addr ,data);
break;
}//?switch_end
return;
}
static void
pxa250_io_write_word (ARMul_State * state, ARMword addr, ARMword data)
{
pxa_ioregnum_t ioregaddr = addr;
//printf("SKYEYE:pxa250_io_write_word: io addr 0x%x, RCNR 0x%x\n",ioregaddr,RCNR);
switch (ioregaddr) {
/*RTC*/ case RCNR:
pxa250_io.rcnr = data;
break;
case RTAR:
pxa250_io.rtar = data;
break;
case RTSR:
pxa250_io.rtsr |= (data & 0xc);
pxa250_io.rtsr &= ~(data & 0x3);
break;
case RTTR:
pxa250_io.rttr = data & 0x3ffffff;
break;
/*OS timer */
case OSCR:
pxa250_io.oscr = data;
break;
case OSMR0:
pxa250_io.osmr0 = data;
break;
case OSMR1:
pxa250_io.osmr1 = data;
break;
case OSMR2:
pxa250_io.osmr2 = data;
break;
case OSMR3:
pxa250_io.osmr3 = data;
break;
case OWER:
pxa250_io.ower |= data & 0x1;
break;
case OSSR:
/* When the status register is updated, the
results are seen immediately in the icpr */
pxa250_io.ossr &= ~(data & 0xf);
pxa250_io.icpr &= ~(0xf << OS_IRQ_SHF);
pxa250_io.icpr |= (pxa250_io.ossr << OS_IRQ_SHF);
break;
case OIER:
pxa250_io.oier = data & 0xf;
break;
/*interrupt control */
//ywc,2004-11-30,for touchscreen use ICPR
case ICPR:
/*read only - see 4.2.2.5 Intel PXA255 Processor Developer's Manual */
break;
case ICMR:
pxa250_io.icmr = data;
break;
case ICLR:
pxa250_io.iclr = data;
break;
//ffuart contril
case FFTHR:
{ /*static tx_cnt=0; */
unsigned char c = data;
/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
skyeye_uart_write(-1, &c, 1, NULL);
/*chy 2004-07-21 from luzhetao: after write char, should set some value */
pxa250_io.ffiir &= ~0x2;
pxa250_io.ffiir |= 0x1;
pxa250_io.fflsr &= ~0x60;
//tx_cnt++;
//pxa250_io.ffier|=0x2;
/*
if(tx_cnt>63){
tx_cnt=0;
pxa250_io.ffiir|=0x2;
pxa250_io.fflsr|=0x60;
refresh_irq(state);
}
*/
//printf("SKYEYE: write FFTHR %x, iir %x,lsr %x, ier %x\n",data, pxa250_io.ffiir,pxa250_io.fflsr,pxa250_io.ffier);
}
break;
case FFIER:
pxa250_io.ffier = data & 0xff;
break;
case FFFCR: //write only
pxa250_io.fffcr = data & 0xc7;
//pxa250_io.ffiir = data & 0xc7 ;
//if(pxa250_io.fffcr & 2
//printf("SKYEYE: write FFFCR %x, but is ffiir %x\n",pxa250_io.fffcr,pxa250_io.ffiir);
break;
case FFLCR:
pxa250_io.fflcr = data & 0xff;
break;
//core clock
case FFMCR:
pxa250_io.ffmcr = data & 0x1f;
break;
//core clock
case CCCR:
pxa250_io.cccr = data & 0x3ff;
break;
case CKEN:
pxa250_io.cken = data & 0x17def;
break;
case OSCC:
pxa250_io.oscc = data & 0x3;
break;
//ywc,2004-11-30,add for pxa's LCD simulation
#if 0
case LCCR0:
tmp = pxa250_io.lccr0;
pxa250_io.lccr0 = data;
if ((!(tmp & LCCR0_ENB)) && (pxa250_io.lccr0 & LCCR0_ENB)) {
if (once)
break;
once++;
/*
printf("\nFDADR0=%x,FDADR1=%x",pxa250_io.fdadr0,pxa250_io.fdadr1);
printf("\n");
pxa250_io.lcd_addr_begin = pxa250_io.fdadr0 + 16*(2+2);
printf("\nlcd_addr_begin=%x",pxa250_io.lcd_addr_begin);
printf("\n");
*/
pxa250_update_lcd (state);
}
break;
case LCCR1:
pxa250_io.lccr1 = data;
break;
case LCCR2:
pxa250_io.lccr2 = data;
break;
case LCCR3:
pxa250_io.lccr3 = data;
break;
case FDADR0:
pxa250_io.fdadr0 = data;
//printf("\nFDADR0=%x",pxa250_io.fdadr0);
//printf("\n");
/*
mbp = bank_ptr(pxa250_io.fdadr0);
if(!mbp){
fprintf(stderr, "No bank at address 0x%x", pxa250_io.fdadr0);
return;
}
fdadr0ADDRESS=(u32 *) &state->mem.rom[mbp - skyeye_config.mem.mem_banks][(pxa250_io.fdadr0 - mbp->addr)];
printf("\n %p",fdadr0ADDRESS);
*/
// printf("\n 0: %x",*((u32 *)fdadr0ADDRESS));
// printf("\n 1: %x",*((u32 *)fdadr0ADDRESS+1));
// printf("\n 2: %x",*((u32 *)fdadr0ADDRESS+2));
// printf("\n 3: %x",*((u32 *)fdadr0ADDRESS+3));
//printf("\n");
break;
case FDADR1:
pxa250_io.fdadr1 = data;
//printf("\nFDADR1=%x",pxa250_io.fdadr1);
//printf("\n");
break;
case FSADR0:
pxa250_io.fsadr0 = data;
//printf("\nFSADR0=%x",pxa250_io.fsadr0);
//printf("\n");
break;
case FSADR1:
pxa250_io.fsadr1 = data;
//printf("\nFSADR1=%x",pxa250_io.fsadr1);
//printf("\n");
break;
#endif
//ywc,2004-11-30,add for pxa's LCD simulation,end
#if 0
case FFIIR: //read only
case FFMSR: //read only no use
case FFSPR: // no use
case FFISR: // no use
#endif
default:
//chy 2003-09-03 if debug, uncommit it
//log_msg("SKYEYE: pxa250_io_write_word: unknown addr 0x%x, reg15 0x%x \n", addr,state->Reg[15]);
;
};
};
void
cs89712_io_write_word (ARMul_State * state, ARMword addr, ARMword data)
{
ARMword tmp;
switch (addr - 0x80000000) {
case SYSCON:
tmp = io.syscon;
io.syscon = data;
/*if ((tmp & LCDEN) != (data & LCDEN)) {
update_lcd(state);
} */
break;
case SYSFLG:
break;
case INTSR:
break;
case INTMR:
io.intmr = data;
extern ARMul_State * state;
cs89712_update_int (state);
break;
case LCDCON:
tmp = io.lcdcon;
io.lcdcon = data;
if ((tmp & (VBUFSIZ | LINELEN | GSEN | GSMD)) !=
(tmp & (VBUFSIZ | LINELEN | GSEN | GSMD))) {
//chy 2005-01-07 no use now
/* update_lcd(state); */
}
break;
case TC1D:
io.tcd[0] = io.tcd_reload[0] = data & 0xffff;
SKYEYE_DBG ("TC1D 0x%x\n", data & 0xffff);
break;
case TC2D:
io.tcd[1] = io.tcd_reload[1] = data & 0xffff;
SKYEYE_DBG ("TC2D 0x%x\n", data & 0xffff);
break;
case UARTDR:
/* The UART writes chars to console */
{
char c = data;
/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
skyeye_uart_write(-1, &c, 1, NULL);
}
break;
/* case BLEOI: printf("BLEOI\n"); break;
case MCEOI: printf("MCEOI\n"); break;
case TEOI: printf("TEOI\n"); break;*/
case TC1EOI:
io.intsr &= ~TC1OI;
extern ARMul_State * state;
cs89712_update_int (state);
SKYEYE_DBG ("TC1EOI\n");
break;
case TC2EOI:
io.intsr &= ~TC2OI;
extern ARMul_State * state;
cs89712_update_int (state);
SKYEYE_DBG ("TC2EOI\n");
break;
//case RTCEOI: printf("RTCEOI\n"); break;
//case UMSEOI: printf("UMSEOI\n"); break;
//case COEOI: printf("COEOI\n"); break;
case 0x2000:
/* Not a real register, for debugging only: */
SKYEYE_DBG ("io_write_word debug: 0x%08lx\n", data);
break;
default:
//chy 2003-07-11: sometime has fault, but linux can continue running !!!!????
//printf("unknown io addr, io_write_word(0x%08x, 0x%08x), pc %x \n", addr, data,state->Reg[15]);
break;
}
}
void
ep7312_io_write_word (void *state, uint32_t addr, uint32_t data)
{
uint32_t tmp;
switch (addr - 0x80000000) {
case SYSCON:
tmp = io.syscon;
io.syscon = data;
//chy 2004-03-11
if ((tmp & LCDEN) != (data & LCDEN)) {
// by ywc 2004-07-07
printf ("\n\n SYSCON:will call ep7312_update_lcd()");
//ep7312_update_lcd (state);
}
break;
case SYSFLG:
break;
case INTSR:
//DBG_PRINT("write INTSR=0x%x\n", data);
io.intsr = data;
// printf("SKYEYE: write INTSR=0x%x\n", io.intsr);
break;
case INTMR:
//DBG_PRINT("write INTMR=0x%x\n", data);
//if(data != 0x2000 && data != 0x2200)
//printf("SKYEYE: write INTMR=0x%x\n", data);
io.intmr = data;
ep7312_update_int (state);
break;
case TC1D:
io.tcd[0] = io.tcd_reload[0] = data & 0xffff;
SKYEYE_DBG ("TC1D 0x%x\n", data & 0xffff);
break;
case TC2D:
io.tcd[1] = io.tcd_reload[1] = data & 0xffff;
SKYEYE_DBG ("TC2D 0x%x\n", data & 0xffff);
break;
case UARTDR:
/* The UART writes chars to console */
{
char c = data;
/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
skyeye_uart_write(-1, &c, 1, NULL);
}
break;
/* case BLEOI: printf("BLEOI\n"); break;
case MCEOI: printf("MCEOI\n"); break;
case TEOI: printf("TEOI\n"); break;*/
case TC1EOI:
io.intsr &= ~TC1OI;
ep7312_update_int (state);
SKYEYE_DBG ("TC1EOI\n");
break;
case TC2EOI:
io.intsr &= ~TC2OI;
ep7312_update_int (state);
SKYEYE_DBG ("TC2EOI\n");
break;
//case RTCEOI: printf("RTCEOI\n"); break;
//case UMSEOI: printf("UMSEOI\n"); break;
//case COEOI: printf("COEOI\n"); break;
case 0x2000:
/* Not a real register, for debugging only: */
SKYEYE_DBG ("io_write_word debug: 0x%08lx\n", data);
break;
default:
//chy 2003-07-11: sometime has fault, but linux can continue running !!!!????
//printf("SKYEYE:unknown io addr, io_write_word(0x%08x, 0x%08x), pc %x \n", addr, data,state->Reg[15]);
break;
}
}
void
lh79520_io_write_word (ARMul_State * state, ARMword addr, ARMword data)
{
ARMword tmp;
if (addr >= VIC_VectAddr && addr <= VIC_VectAddr + 0x3c) {
// printf("%s VectAddr(%x %x)\n", __func__, addr, data);
return;
}
if (addr >= VIC_VectCntl && addr <= VIC_VectCntl + 0x3c) {
// printf("%s VectCntl(%x %x)\n", __func__, addr, data);
return;
}
if (addr >= DMAC_PHYS && addr < RCPC_PHYS) {
// printf("%s DMAC(%x %x)\n", __func__, addr, data);
return;
}
switch (addr) {
case VIC_IntSelect:
case IOCON_MiscMux:
case IOCON_UARTMux:
case RCPC_PHYS:
case RCPC_idString:
case RCPC_intClear:
case RCPC_intConfig:
case RCPC_HCLKPrescale:
case RCPC_periphClkCtrl:
case TIMER0_LOAD:
case TIMER0_VALUE:
case TIMER1_LOAD:
case TIMER1_VALUE:
case TIMER1_CONTROL:
case TIMER1_CLEAR:
case TIMER2_CONTROL:
case TIMER3_CONTROL:
case UART1_PHYS + UARTIBRD:
case UART1_PHYS + UARTLCR_H:
// printf("%s(%x %x)\n", __func__, addr, data);
break;
case TIMER0_CONTROL:
io.tcd_ctrl[0] = data;
break;
case TIMER0_CLEAR:
io.intsr &= ~TC1OI;
lh79520_update_int (state);
break;
case VIC_IntEnable:
io.intmr = data;
lh79520_update_int (state);
break;
case VIC_IntEnClear:
io.intmr &= ~data;
lh79520_update_int (state);
break;
case UART0_PHYS:
case UART1_PHYS:
/* The UART writes chars to console */
{
char c = data;
/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
skyeye_uart_write(-1, &c, 1, NULL);
}
break;
case UART1_PHYS + UARTCR:
io.uartcr = data;
break;
case UART1_PHYS + UARTIMSC: //5: TXIM 4: RXIM
io.uartimsc = data;
if (data & AMBA_UART_IS_TX)
io.uartmis |= AMBA_UART_IS_TX;
else
io.uartmis &= ~AMBA_UART_IS_TX;
UART2VIC (state);
break;
default:
//chy 2003-07-11: sometime has fault, but linux can continue running !!!!????
printf ("SKYEYE:unknown io addr, %s(0x%08x, 0x%08x), pc %x \n", __func__, addr, data, state->Reg[15]);
break;
}
}
} void
s3c4510b_io_write_word (ARMul_State * state, ARMword addr, ARMword data)
{
switch (addr) {
case SYSCFG:
io.syscfg = data;
break;
case CLKCON:
io.clkcon = data;
break;
case INTMOD:
io.intmod = data;
break;
case INTPND:
/*when write bit 1, we clear apropiate pendind bit.
* */
io.intpnd &= (~data & INT_MASK_INIT);
break;
case INTMSK:
io.intmsk = data;
break;
case INTOFFSET:
case INTPNDTST:
io.intpndtst = io.intpnd = data;
break;
case INTOSET_FIQ:
io.intoset_fiq = data;
break;
case INTOSET_IRQ:
io.intoset_irq = data;
break;
/*UART*/ case ULCON0:
io.ulcon0 = data;
break;
case ULCON1:
io.ulcon1 = data;
break;
case UCON0:
io.ucon0 = data;
break;
case UCON1:
io.ucon1 = data;
break;
case USTAT0:
io.ustat0 = data;
break;
case USTAT1:
io.ustat1 = data;
break;
case UTXBUF0:
{
char c = data;
/* 2007-01-18 modified by Anthony Lee : for new uart device frame */
skyeye_uart_write(-1, &c, 1, NULL);
io.ustat0 |= (UART_LSR_THRE | UART_LSR_TEMT);
if ((io.ucon0 & 0xc) == 0xc) { /*enable interrupt */
s3c4510b_set_interrupt (INT_UARTTX0);
extern ARMul_State * state;
s3c4510b_update_int (state);
}
}
break;
case UTXBUF1:
break;
case UBRDIV0:
io.ubrdiv0 = data;
break;
case UBRDIV1:
io.ubrdiv1 = data;
break;
/*Timer */
case TMOD:
io.tmod = data;
if (ENABLE_TIMER0)
io.tcnt0 = io.tdata0;
if (ENABLE_TIMER1)
io.tcnt1 = io.tdata1;
break;
case TDATA0:
if (!ENABLE_TIMER0)
io.tdata0 = data;
/*we manually set tdata0 register, uclinux's data is so big */
io.tdata0 = 0xfff;
break;
case TDATA1:
//if (!ENABLE_TIMER1)
io.tdata1 = data;
break;
case TCNT0:
io.tcnt0 = data;
break;
case TCNT1:
io.tcnt1 = data;
break;
default:
SKYEYE_DBG ("%s(0x%08x) = 0x%08x\n", __FUNCTION__, addr,
data);
break;
}
}